Liu, Qiyuan.
Design Techniques for Mash Continuous-Time Delta-Sigma Modulators [electronic resource] / by Qiyuan Liu, Alexander Edward, Carlos Briseno-Vidrios, Jose Silva-Martinez. - 1st ed. 2018. - XVI, 208 p. 184 illus., 71 illus. in color. online resource.
Introduction -- Analog-To-Digital and Digital-To-Analog Converters -- Delta-Sigma Modulators -- Design Considerations Of Mash CT-ΔΣM -- A 43 mW MASH 2-2 CT ΔΣ Modulator Attaining 74.4/75.8/76.8 dB of SNDR/SNR/DR and 50 MHz of BW in 40nm CMOS -- A 50-MHz BW 67.3-dB SNDR MASH 1-1-1 CT ΔΣ Modulator with FIR DAC and Encoder-Embedded Loop-Unrolling Quantizer in 40-nm CMOS -- A 4-Bit Continuous-Time ΔΣ Modulator with Fully Digital Quantizer Noise Reduction Algorithm Employing a 7-bit Quantizer -- Conclusion.
This book describes a circuit architecture for converting real analog signals into a digital format, suitable for digital signal processors. This architecture, referred to as multi-stage noise-shaping (MASH) Continuous-Time Sigma-Delta Modulators (CT-ΔΣM), has the potential to provide better digital data quality and achieve better data rate conversion with lower power consumption. The authors not only cover MASH continuous-time sigma delta modulator fundamentals, but also provide a literature review that will allow students, professors, and professionals to catch up on the latest developments in related technology.
9783319772257
10.1007/978-3-319-77225-7 doi
Electronic circuits.
Microprocessors.
Computer architecture.
Signal processing.
Electronic Circuits and Systems.
Processor Architectures.
Signal, Speech and Image Processing .
TK7867-7867.5
621.3815
Design Techniques for Mash Continuous-Time Delta-Sigma Modulators [electronic resource] / by Qiyuan Liu, Alexander Edward, Carlos Briseno-Vidrios, Jose Silva-Martinez. - 1st ed. 2018. - XVI, 208 p. 184 illus., 71 illus. in color. online resource.
Introduction -- Analog-To-Digital and Digital-To-Analog Converters -- Delta-Sigma Modulators -- Design Considerations Of Mash CT-ΔΣM -- A 43 mW MASH 2-2 CT ΔΣ Modulator Attaining 74.4/75.8/76.8 dB of SNDR/SNR/DR and 50 MHz of BW in 40nm CMOS -- A 50-MHz BW 67.3-dB SNDR MASH 1-1-1 CT ΔΣ Modulator with FIR DAC and Encoder-Embedded Loop-Unrolling Quantizer in 40-nm CMOS -- A 4-Bit Continuous-Time ΔΣ Modulator with Fully Digital Quantizer Noise Reduction Algorithm Employing a 7-bit Quantizer -- Conclusion.
This book describes a circuit architecture for converting real analog signals into a digital format, suitable for digital signal processors. This architecture, referred to as multi-stage noise-shaping (MASH) Continuous-Time Sigma-Delta Modulators (CT-ΔΣM), has the potential to provide better digital data quality and achieve better data rate conversion with lower power consumption. The authors not only cover MASH continuous-time sigma delta modulator fundamentals, but also provide a literature review that will allow students, professors, and professionals to catch up on the latest developments in related technology.
9783319772257
10.1007/978-3-319-77225-7 doi
Electronic circuits.
Microprocessors.
Computer architecture.
Signal processing.
Electronic Circuits and Systems.
Processor Architectures.
Signal, Speech and Image Processing .
TK7867-7867.5
621.3815