Constraining Designs for Synthesis and Timing Analysis (Record no. 52156)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 03345nam a22004935i 4500 |
| 001 - CONTROL NUMBER | |
| control field | 978-1-4614-3269-2 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20200420220225.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 130507s2013 xxu| s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9781461432692 |
| -- | 978-1-4614-3269-2 |
| 082 04 - CLASSIFICATION NUMBER | |
| Call Number | 621.3815 |
| 100 1# - AUTHOR NAME | |
| Author | Gangadharan, Sridhar. |
| 245 10 - TITLE STATEMENT | |
| Title | Constraining Designs for Synthesis and Timing Analysis |
| Sub Title | A Practical Guide to Synopsys Design Constraints (SDC) / |
| 300 ## - PHYSICAL DESCRIPTION | |
| Number of Pages | XXVII, 226 p. |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Remark 2 | Introduction -- Synthesis Basics -- Timing Analysis and Constraints -- SDC Extensions through Tcl -- Clocks -- Generated Clocks -- Clock Groups -- Other Clock Characteristics -- Port Delays -- Completing Port Constraints -- False Paths -- Multi Cycle Paths -- Combinatorial Paths -- Modal Analysis -- Managing Your Constraints -- Miscellaneous SDC Commands -- XDC: Xilinx Extensions To SDC. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc | This book serves as a hands-on guide to timing constraints in integrated circuit design.  Readers will learn to maximize performance of their IC designs, by specifying timing requirements correctly.  Coverage includes key aspects of the design flow impacted by timing constraints, including synthesis, static timing analysis and placement and routing.  Concepts needed for specifying timing requirements are explained in detail and then applied to specific stages in the design flow, all within the context of Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints.  �         Provides a hands-on guide to synthesis and timing analysis, using Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints; �         Includes key topics of interest to a synthesis, static timing analysis or  place and route engineer; �         Explains which constraints command to use for ease of maintenance and reuse, given several options possible to achieve the same effect on timing; �         Explains fundamental concepts and provides exact command syntax. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Churiwala, Sanjay. |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | http://dx.doi.org/10.1007/978-1-4614-3269-2 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | eBooks |
| 264 #1 - | |
| -- | New York, NY : |
| -- | Springer New York : |
| -- | Imprint: Springer, |
| -- | 2013. |
| 336 ## - | |
| -- | text |
| -- | txt |
| -- | rdacontent |
| 337 ## - | |
| -- | computer |
| -- | c |
| -- | rdamedia |
| 338 ## - | |
| -- | online resource |
| -- | cr |
| -- | rdacarrier |
| 347 ## - | |
| -- | text file |
| -- | |
| -- | rda |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Engineering. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Microprocessors. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Electronics. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Microelectronics. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Electronic circuits. |
| 650 14 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Engineering. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Circuits and Systems. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Electronics and Microelectronics, Instrumentation. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Processor Architectures. |
| 912 ## - | |
| -- | ZDB-2-ENG |
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