Designing 2D and 3D Network-on-Chip Architectures (Record no. 52234)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 03329nam a22005175i 4500 |
| 001 - CONTROL NUMBER | |
| control field | 978-1-4614-4274-5 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20200420220226.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 131008s2014 xxu| s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9781461442745 |
| -- | 978-1-4614-4274-5 |
| 082 04 - CLASSIFICATION NUMBER | |
| Call Number | 621.3815 |
| 100 1# - AUTHOR NAME | |
| Author | Tatas, Konstantinos. |
| 245 10 - TITLE STATEMENT | |
| Title | Designing 2D and 3D Network-on-Chip Architectures |
| 300 ## - PHYSICAL DESCRIPTION | |
| Number of Pages | XIII, 265 p. 144 illus., 79 illus. in color. |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Remark 2 | Part I: Network-on-Chip Design Methodology -- Network-on-Chip Technology: A Paradigm Shift -- NoC Modeling and Topology Exploration -- Communication Architecture -- Power and Thermal Effects and Management -- NoC-based System Integration -- NoC Verification and Testing -- The Spidergon STNoC -- Middleware Memory Management in NoC -- On Designing 3-D Platforms -- The SYSMANTIC NoC Design and Prototyping Framework -- Part II: Suggested Projects.-  Projects on Network-on Chip. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc | This book covers key concepts in the design of 2D and 3D Network-on-Chip interconnect.  It highlights design challenges and discusses fundamentals of NoC technology, including architectures, algorithms and tools.  Coverage focuses on topology exploration for both 2D and 3D NoCs, routing algorithms, NoC router design, NoC-based system integration, verification and testing, and NoC reliabilty.  Case studies are used to illuminate new design methodologies.  �         Describes essential theory, practice and state-of-the-art applications of 2D and 3D Network-on-Chip interconnect; �         Enables readers to exploit parallelism in processor architecture, with interconnect design that is efficient in terms of energy and performance; �         Covers topics not available in other books, such as NoC and distributed memory organization, dynamic memory management and abstract data type support in many-core platforms, and distributed hierarchical power management. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Siozios, Kostas. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Soudris, Dimitrios. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Jantsch, Axel. |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | http://dx.doi.org/10.1007/978-1-4614-4274-5 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | eBooks |
| 264 #1 - | |
| -- | New York, NY : |
| -- | Springer New York : |
| -- | Imprint: Springer, |
| -- | 2014. |
| 336 ## - | |
| -- | text |
| -- | txt |
| -- | rdacontent |
| 337 ## - | |
| -- | computer |
| -- | c |
| -- | rdamedia |
| 338 ## - | |
| -- | online resource |
| -- | cr |
| -- | rdacarrier |
| 347 ## - | |
| -- | text file |
| -- | |
| -- | rda |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Engineering. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Microprocessors. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Electronics. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Microelectronics. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Electronic circuits. |
| 650 14 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Engineering. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Circuits and Systems. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Electronics and Microelectronics, Instrumentation. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Processor Architectures. |
| 912 ## - | |
| -- | ZDB-2-ENG |
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