IP Cores Design from Specifications to Production (Record no. 52840)
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000 -LEADER | |
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fixed length control field | 03660nam a22005055i 4500 |
001 - CONTROL NUMBER | |
control field | 978-3-319-22035-2 |
005 - DATE AND TIME OF LATEST TRANSACTION | |
control field | 20200420221255.0 |
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
fixed length control field | 150827s2016 gw | s |||| 0|eng d |
020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
ISBN | 9783319220352 |
-- | 978-3-319-22035-2 |
082 04 - CLASSIFICATION NUMBER | |
Call Number | 621.3815 |
100 1# - AUTHOR NAME | |
Author | Mohamed, Khaled Salah. |
245 10 - TITLE STATEMENT | |
Title | IP Cores Design from Specifications to Production |
Sub Title | Modeling, Verification, Optimization, and Protection / |
300 ## - PHYSICAL DESCRIPTION | |
Number of Pages | IX, 154 p. 153 illus., 115 illus. in color. |
490 1# - SERIES STATEMENT | |
Series statement | Analog Circuits and Signal Processing, |
505 0# - FORMATTED CONTENTS NOTE | |
Remark 2 | 1. Introduction -- 2. IP Cores Design from Specifications to Production: Modeling, Verification, Optimization, and Protection -- 3. Analyzing the Trade-off between Different Memory Cores and Controllers -- 4. SOC BUSES AND PERIPHERALS: FEATURES AND ARCHITECTURES -- 5. Verilog for Implementation and Verification -- 6. New Trends in SoC Verification: UVM, Bug Localization, Scan-Chain-Based Methodology, GA-Based Test Generation -- 7. Conclusions. |
520 ## - SUMMARY, ETC. | |
Summary, etc | This book describes the life cycle process of IP cores, from specification to production, including IP modeling, verification, optimization, and protection. Various trade-offs in the design process are discussed, including  those associated with many of the most common memory cores, controller IPs  and system-on-chip (SoC) buses. Readers will also benefit from the author's practical coverage of new verification methodologies. such as bug localization, UVM, and scan-chain.  A SoC case study is presented to compare traditional verification with the new verification methodologies. �         Discusses the entire life cycle process of IP cores, from specification to production, including IP modeling, verification, optimization, and protection; �         Introduce a deep introduction for Verilog for both implementation and verification point of view.  �         Demonstrates how to use IP in applications such as memory controllers and SoC buses. �         Describes a new verification methodology called bug localization; �         Presents a novel scan-chain methodology for RTL debugging; �         Enables readers to employ UVM methodology in straightforward, practical terms. |
856 40 - ELECTRONIC LOCATION AND ACCESS | |
Uniform Resource Identifier | http://dx.doi.org/10.1007/978-3-319-22035-2 |
942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
Koha item type | eBooks |
264 #1 - | |
-- | Cham : |
-- | Springer International Publishing : |
-- | Imprint: Springer, |
-- | 2016. |
336 ## - | |
-- | text |
-- | txt |
-- | rdacontent |
337 ## - | |
-- | computer |
-- | c |
-- | rdamedia |
338 ## - | |
-- | online resource |
-- | cr |
-- | rdacarrier |
347 ## - | |
-- | text file |
-- | |
-- | rda |
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
-- | Engineering. |
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
-- | Microprocessors. |
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
-- | Electronics. |
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
-- | Microelectronics. |
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
-- | Electronic circuits. |
650 14 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
-- | Engineering. |
650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
-- | Circuits and Systems. |
650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
-- | Processor Architectures. |
650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
-- | Electronics and Microelectronics, Instrumentation. |
830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE | |
-- | 1872-082X |
912 ## - | |
-- | ZDB-2-ENG |
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