Automated Technology for Verification and Analysis (Record no. 52902)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 04492nam a22005895i 4500 |
| 001 - CONTROL NUMBER | |
| control field | 978-3-319-11936-6 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20200420221256.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 141024s2014 gw | s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9783319119366 |
| -- | 978-3-319-11936-6 |
| 082 04 - CLASSIFICATION NUMBER | |
| Call Number | 005.1 |
| 245 10 - TITLE STATEMENT | |
| Title | Automated Technology for Verification and Analysis |
| Sub Title | 12th International Symposium, ATVA 2014, Sydney, NSW, Australia, November 3-7, 2014, Proceedings / |
| 300 ## - PHYSICAL DESCRIPTION | |
| Number of Pages | XXIV, 430 p. 109 illus. |
| 490 1# - SERIES STATEMENT | |
| Series statement | Lecture Notes in Computer Science, |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Remark 2 | Verifying Communicating Multi-pushdown Systems via Split-Width -- Booster: An Acceleration-Based Verification Framework for Array Programs -- A Bounded Model Checker for SPARK Programs -- Acceleration of Affine Hybrid Transformations -- A Mechanized Proof of Loop Freedom of the (Untimed) AODV Routing Protocol -- Quantitative Verification of Weighted Kripke Structures -- Formal Safety Assessment via Contract-Based Design -- Verification of Markov Decision Processes Using Learning Algorithms -- Test Coverage Estimation Using Threshold Accepting -- On Time with Minimal Expected Cost! -- Fast Debugging of PRISM Models -- ACME: Automata with Counters, Monoids and Equivalence (Tool Paper).-Modelling and Analysis of Markov Reward Automata -- Extensional Crisis and Proving Identity -- Deciding Entailments in Inductive Separation Logic with Tree Automata -- Liveness Analysis for Parameterised Boolean Equation Systems -- Rabinizer 3: Safraless Translation of LTL to Small Deterministic Automata -- PeCAn: Compositional Verification of Petri Nets Made Easy -- The Context-Freeness Problem Is coNP-Complete for Flat Counter Systems -- Efficiently and Completely Verifying Synchronized Consistency Models -- Symmetry Reduction in Infinite Games with Finite Branching -- Incremental Encoding and Solving of Cardinality Constraints -- Formal Verification of Skiplists with Arbitrary Many Levels -- Using Flow Specifications of Parameterized Cache Coherence Protocols for Verifying Deadlock Freedom -- A Game-Theoretic Approach to Simulation of Data-Parameterized Systems -- Nested Reachability Approximation for Discrete-Time Markov Chains with Univariate Parameters -- Symbolic Memory with Pointers -- Trace Abstraction Refinement for Timed Automata -- Statistically Sound Verification and Optimization for Complex Systems. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc | This book constitutes the proceedings of the 12th International Symposium on Automated Technology for Verification and Analysis, ATVA 2014, held in Sydney, Australia, in November 2014. The 29 revised papers presented in this volume were carefully reviewed and selected from 76 submissions. They show current research on theoretical and practical aspects of automated analysis, verification and synthesis by providing an international forum for interaction among the researchers in academia and industry. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Cassez, Franck. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Raskin, Jean-Fran�cois. |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | http://dx.doi.org/10.1007/978-3-319-11936-6 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | eBooks |
| 264 #1 - | |
| -- | Cham : |
| -- | Springer International Publishing : |
| -- | Imprint: Springer, |
| -- | 2014. |
| 336 ## - | |
| -- | text |
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| -- | computer |
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| -- | rdamedia |
| 338 ## - | |
| -- | online resource |
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| -- | rdacarrier |
| 347 ## - | |
| -- | text file |
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| -- | rda |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Computer science. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Computer communication systems. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Computer programming. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Software engineering. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Programming languages (Electronic computers). |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Computer logic. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Mathematical logic. |
| 650 14 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Computer Science. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Software Engineering. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Programming Techniques. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Computer Communication Networks. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Logics and Meanings of Programs. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Programming Languages, Compilers, Interpreters. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Mathematical Logic and Formal Languages. |
| 830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE | |
| -- | 0302-9743 ; |
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