Multiple Constant Multiplication Optimizations for Field Programmable Gate Arrays (Record no. 52918)

000 -LEADER
fixed length control field 03365nam a22004815i 4500
001 - CONTROL NUMBER
control field 978-3-658-13323-8
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20200420221256.0
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 160413s2016 gw | s |||| 0|eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
ISBN 9783658133238
-- 978-3-658-13323-8
082 04 - CLASSIFICATION NUMBER
Call Number 621.3
100 1# - AUTHOR NAME
Author Kumm, Martin.
245 10 - TITLE STATEMENT
Title Multiple Constant Multiplication Optimizations for Field Programmable Gate Arrays
300 ## - PHYSICAL DESCRIPTION
Number of Pages XXXIII, 206 p. 47 illus.
505 0# - FORMATTED CONTENTS NOTE
Remark 2 Heuristic and ILP-Based Optimal Solutions for the Pipelined Multiple Constant Multiplication Problem -- Methods to Integrate Embedded Multipliers, LUT-Based Constant Multipliers and Ternary (3-Input) Adders -- An Optimized Multiple Constant Multiplication Architecture Using Floating Point Arithmetic. .
520 ## - SUMMARY, ETC.
Summary, etc This work covers field programmable gate array (FPGA)-specific optimizations of circuits computing the multiplication of a variable by several constants, commonly denoted as multiple constant multiplication (MCM). These optimizations focus on low resource usage but high performance. They comprise the use of fast carry-chains in adder-based constant multiplications including ternary (3-input) adders as well as the integration of look-up table-based constant multipliers and embedded multipliers to get the optimal mapping to modern FPGAs. The proposed methods can be used for the efficient implementation of digital filters, discrete transforms and many other circuits in the domain of digital signal processing, communication and image processing. Contents Heuristic and ILP-Based Optimal Solutions for the Pipelined Multiple Constant Multiplication Problem Methods to Integrate Embedded Multipliers, LUT-Based Constant Multipliers and Ternary (3-Input) Adders An Optimized Multiple Constant Multiplication Architecture Using Floating Point Arithmetic Target Groups Researchers and students of electrical engineering and computer science Practitioners in the area of FPGAs and signal processing or digital arithmetic The Author Martin Kumm is working as a postdoctoral researcher at the University of Kassel. His current research interests are digital arithmetic, digital signal processing and discrete optimization, all in the context of field programmable gate arrays. .
856 40 - ELECTRONIC LOCATION AND ACCESS
Uniform Resource Identifier http://dx.doi.org/10.1007/978-3-658-13323-8
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Koha item type eBooks
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-- Wiesbaden :
-- Springer Fachmedien Wiesbaden :
-- Imprint: Springer Vieweg,
-- 2016.
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650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Engineering.
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-- Computer hardware.
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-- Applied mathematics.
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-- Engineering mathematics.
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-- Electrical engineering.
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-- Engineering.
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-- Electrical Engineering.
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-- Computer Hardware.
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-- Appl.Mathematics/Computational Methods of Engineering.
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-- ZDB-2-ENG

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