System Level ESD Protection (Record no. 55253)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 03442nam a22004815i 4500 |
| 001 - CONTROL NUMBER | |
| control field | 978-3-319-03221-4 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20200421111706.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 140321s2014 gw | s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9783319032214 |
| -- | 978-3-319-03221-4 |
| 082 04 - CLASSIFICATION NUMBER | |
| Call Number | 621.3815 |
| 100 1# - AUTHOR NAME | |
| Author | Vashchenko, Vladislav. |
| 245 10 - TITLE STATEMENT | |
| Title | System Level ESD Protection |
| 300 ## - PHYSICAL DESCRIPTION | |
| Number of Pages | XVIII, 320 p. 295 illus., 12 illus. in color. |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Remark 2 | System 1 Level ESD design -- System Level Test Methods -- On-Chip System Level ESD Devices and Clamps -- Latch-up at System-Level Stress -- IC and Systemn ESD Co-Design. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc | This book addresses key aspects of analog integrated circuits and systems design related to system level electrostatic discharge (ESD) protection. It is an invaluable reference for anyone developing systems-on-chip (SoC) and systems-on-package (SoP), integrated with system-level ESD protection. The book focuses on both the design of semiconductor integrated circuit (IC) components with embedded, on-chip system level protection and IC-system co-design. The readers will be enabled to bring the system level ESD protection solutions to the level of integrated circuits, thereby reducing or completely eliminating the need for additional, discrete components on the printed circuit board (PCB) and meeting system-level ESD requirements. The authors take a systematic approach, based on IC-system ESD protection co-design. A detailed description of the available IC-level ESD testing methods is provided, together with a discussion of the correlation between IC-level and system-level ESD testing methods. The IC-level ESD protection design is demonstrated with representative case studies which are analyzed with various numerical simulations and ESD testing. The overall methodology for IC-system ESD co-design is presented as a step-by-step procedure that involves both ESD testing and numerical simulations. • Provides a systematic approach for on-chip ESD protection design for system-level IC pins; • Describes a system-level co-design methodology, which uses external system level ESD protection components, together with on-chip ESD protection structure; • Includes a comprehensive description of wafer- level and component-level test methodologies and numerical simulations. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Scholz, Mirko. |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | http://dx.doi.org/10.1007/978-3-319-03221-4 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | eBooks |
| 264 #1 - | |
| -- | Cham : |
| -- | Springer International Publishing : |
| -- | Imprint: Springer, |
| -- | 2014. |
| 336 ## - | |
| -- | text |
| -- | txt |
| -- | rdacontent |
| 337 ## - | |
| -- | computer |
| -- | c |
| -- | rdamedia |
| 338 ## - | |
| -- | online resource |
| -- | cr |
| -- | rdacarrier |
| 347 ## - | |
| -- | text file |
| -- | |
| -- | rda |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Engineering. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Electronic circuits. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Electronics. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Microelectronics. |
| 650 14 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Engineering. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Circuits and Systems. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Electronic Circuits and Devices. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Electronics and Microelectronics, Instrumentation. |
| 912 ## - | |
| -- | ZDB-2-ENG |
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