Source-Synchronous Networks-On-Chip (Record no. 57993)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 02883nam a22005055i 4500 |
| 001 - CONTROL NUMBER | |
| control field | 978-1-4614-9405-8 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20200421112231.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 131113s2014 xxu| s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9781461494058 |
| -- | 978-1-4614-9405-8 |
| 082 04 - CLASSIFICATION NUMBER | |
| Call Number | 621.3815 |
| 100 1# - AUTHOR NAME | |
| Author | Mandal, Ayan. |
| 245 10 - TITLE STATEMENT | |
| Title | Source-Synchronous Networks-On-Chip |
| Sub Title | Circuit and Architectural Interconnect Modeling / |
| 300 ## - PHYSICAL DESCRIPTION | |
| Number of Pages | XIII, 143 p. 95 illus., 10 illus. in color. |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Remark 2 | Introduction -- Clock Distribution for fast Networks-on-Chip -- Fast Network-on-Chip Design -- Fast On-Chip Data transfer using Sinusoid Signals -- Conclusion and Future Work. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc | This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized. Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic. • Describes novel methods for high-speed network-on-chip (NoC) design; • Enables readers to understand NoC design from both circuit and architectural levels; • Provides circuit-level details of the NoC (including clocking, router design), along with a high-speed, resonant clocking style which is used in the NoC; • Includes architectural simulations of the NoC, demonstrating significantly superior performance over the state-of-the-art. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Khatri, Sunil P. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Mahapatra, Rabi. |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | http://dx.doi.org/10.1007/978-1-4614-9405-8 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | eBooks |
| 264 #1 - | |
| -- | New York, NY : |
| -- | Springer New York : |
| -- | Imprint: Springer, |
| -- | 2014. |
| 336 ## - | |
| -- | text |
| -- | txt |
| -- | rdacontent |
| 337 ## - | |
| -- | computer |
| -- | c |
| -- | rdamedia |
| 338 ## - | |
| -- | online resource |
| -- | cr |
| -- | rdacarrier |
| 347 ## - | |
| -- | text file |
| -- | |
| -- | rda |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Engineering. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Microprocessors. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Electronics. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Microelectronics. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Electronic circuits. |
| 650 14 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Engineering. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Circuits and Systems. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Processor Architectures. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Electronics and Microelectronics, Instrumentation. |
| 912 ## - | |
| -- | ZDB-2-ENG |
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