UTLEON3: Exploring Fine-Grain Multi-Threading in FPGAs (Record no. 59207)
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000 -LEADER | |
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fixed length control field | 03202nam a22005295i 4500 |
001 - CONTROL NUMBER | |
control field | 978-1-4614-2410-9 |
005 - DATE AND TIME OF LATEST TRANSACTION | |
control field | 20200421112557.0 |
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
fixed length control field | 121026s2013 xxu| s |||| 0|eng d |
020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
ISBN | 9781461424109 |
-- | 978-1-4614-2410-9 |
082 04 - CLASSIFICATION NUMBER | |
Call Number | 621.3815 |
100 1# - AUTHOR NAME | |
Author | Daněk, Martin. |
245 10 - TITLE STATEMENT | |
Title | UTLEON3: Exploring Fine-Grain Multi-Threading in FPGAs |
300 ## - PHYSICAL DESCRIPTION | |
Number of Pages | XVIII, 222 p. |
505 0# - FORMATTED CONTENTS NOTE | |
Remark 2 | Introduction -- The LEON3 Processor -- Microthreaded Extensions -- The Basic UTLEON3 Architecture.- UTLEON3 Programming by Example -- UTLEON3 Implementation Details -- Execution Effieciency of the Microthread Pipeline.- Hardware Families of Threads -- I/O and Interrupt Handling in the Microthread Mode -- The IU3 Pipeline -- Excerpts from the LEON3 Instruction Set -- Relevant LEON3 Registers and Address Space Identifiers.- Scheduler Example -- Used Resources -- Tutorial. |
520 ## - SUMMARY, ETC. | |
Summary, etc | This book describes a specification, microarchitecture, VHDL implementation and evaluation of a SPARC v8 CPU with fine-grain multi-threading, called micro-threading. The CPU, named UTLEON3, is an alternative platform for exploring CPU multi-threading that is compatible with the industry-standard GRLIB package. The processor microarchitecture was designed to map in an efficient way the data-flow scheme on a classical von Neumann pipelined processing used in common processors, while retaining full binary compatibility with existing legacy programs.  Describes and documents a working SPARC v8, with fine-grain multithreading and fast context switch; Provides VHDL sources for the described processor; Describes a latency-tolerant framework for coupling hardware accelerators to microthreaded processor pipelines; Includes programming by example in the micro-threaded assembly language.    . |
700 1# - AUTHOR 2 | |
Author 2 | Kafka, Leoš. |
700 1# - AUTHOR 2 | |
Author 2 | Kohout, Luk�aš. |
700 1# - AUTHOR 2 | |
Author 2 | S�ykora, Jaroslav. |
700 1# - AUTHOR 2 | |
Author 2 | Bartosinski, Roman. |
856 40 - ELECTRONIC LOCATION AND ACCESS | |
Uniform Resource Identifier | http://dx.doi.org/10.1007/978-1-4614-2410-9 |
942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
Koha item type | eBooks |
264 #1 - | |
-- | New York, NY : |
-- | Springer New York : |
-- | Imprint: Springer, |
-- | 2013. |
336 ## - | |
-- | text |
-- | txt |
-- | rdacontent |
337 ## - | |
-- | computer |
-- | c |
-- | rdamedia |
338 ## - | |
-- | online resource |
-- | cr |
-- | rdacarrier |
347 ## - | |
-- | text file |
-- | |
-- | rda |
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
-- | Engineering. |
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
-- | Microprocessors. |
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
-- | Electronics. |
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
-- | Microelectronics. |
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
-- | Electronic circuits. |
650 14 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
-- | Engineering. |
650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
-- | Circuits and Systems. |
650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
-- | Processor Architectures. |
650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
-- | Electronics and Microelectronics, Instrumentation. |
912 ## - | |
-- | ZDB-2-ENG |
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