Transient-induced latchup in CMOS integrated circuits / (Record no. 59642)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 04598nam a2200937 i 4500 |
| 001 - CONTROL NUMBER | |
| control field | 5453758 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20200421114118.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 151221s2010 njua ob 001 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9780470824092 |
| -- | electronic |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| -- | |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| -- | electronic |
| 082 04 - CLASSIFICATION NUMBER | |
| Call Number | 621.39/5 |
| 100 1# - AUTHOR NAME | |
| Author | Ker, Ming-Dou, |
| 245 10 - TITLE STATEMENT | |
| Title | Transient-induced latchup in CMOS integrated circuits / |
| 300 ## - PHYSICAL DESCRIPTION | |
| Number of Pages | 1 PDF (xiii, 249 pages) : |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Remark 2 | Physical Mechanism of TLU under the System-Level ESD Test -- Component-Level Measurement for TLU under System-Level ESD Considerations -- TLU Dependency on Power-Pin Damping Frequency and Damping Factor in CMOS Integrated Circuits -- TLU in CMOS ICs in the Electrical Fast Transient Test -- Methodology on Extracting Compact Layout Rules for Latchup Prevention -- Special Layout Issues for Latchup Prevention -- TLU Prevention in Power-Rail ESD Clamp Circuits -- Appendix A: Practical Application Extractions of Latchup Design Rules in a 0.18-mm 1.8 V/3.3V Silicided CMOS Process. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc | "Transient-Induced Latchup in CMOS Integrated Circuits equips the practicing engineer with all the tools needed to address this regularly occurring problem while becoming more proficient at IC layout. Ker and Hsu introduce the phenomenon and basic physical mechanism of latchup, explaining the critical issues that have resurfaced for CMOS technologies. Once readers can gain an understanding of the standard practices for TLU, Ker and Hsu discuss the physical mechanism of TLU under a system-level ESD test, while introducing an efficient component-level TLU measurement setup. The authors then present experimental methodologies to extract safe and area-efficient compact layout rules for latchup prevention, including layout rules for I/O cells, internal circuits, and between I/O and internal circuits. The book concludes with an appendix giving a practical example of extracting layout rules and guidelines for latchup prevention in a 0.18-micrometer 1.8V/3.3V silicided CMOS process."--Publisher's description. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| General subdivision | Defects. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| General subdivision | Reliability. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Hsu, Sheng-Fu. |
| 856 42 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | http://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=5453758 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | eBooks |
| 264 #1 - | |
| -- | Singapore ; |
| -- | Wiley, |
| -- | c2009. |
| 264 #2 - | |
| -- | [Piscataqay, New Jersey] : |
| -- | IEEE Xplore, |
| -- | [2010] |
| 336 ## - | |
| -- | text |
| -- | rdacontent |
| 337 ## - | |
| -- | electronic |
| -- | isbdmedia |
| 338 ## - | |
| -- | online resource |
| -- | rdacarrier |
| 588 ## - | |
| -- | Description based on PDF viewed 12/21/2015. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Metal oxide semiconductors, Complementary |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Metal oxide semiconductors, Complementary |
| 695 ## - | |
| -- | CMOS integrated circuits |
| 695 ## - | |
| -- | CMOS process |
| 695 ## - | |
| -- | CMOS technology |
| 695 ## - | |
| -- | Clamps |
| 695 ## - | |
| -- | Conferences |
| 695 ## - | |
| -- | Current measurement |
| 695 ## - | |
| -- | Damping |
| 695 ## - | |
| -- | Electric breakdown |
| 695 ## - | |
| -- | Electrical resistance measurement |
| 695 ## - | |
| -- | Electrostatic discharge |
| 695 ## - | |
| -- | Frequency measurement |
| 695 ## - | |
| -- | Guidelines |
| 695 ## - | |
| -- | Indexes |
| 695 ## - | |
| -- | Integrated circuit modeling |
| 695 ## - | |
| -- | Integrated circuit reliability |
| 695 ## - | |
| -- | Inverters |
| 695 ## - | |
| -- | Junctions |
| 695 ## - | |
| -- | Layout |
| 695 ## - | |
| -- | Logic gates |
| 695 ## - | |
| -- | MOS devices |
| 695 ## - | |
| -- | Noise |
| 695 ## - | |
| -- | Performance evaluation |
| 695 ## - | |
| -- | Pins |
| 695 ## - | |
| -- | Pulse measurements |
| 695 ## - | |
| -- | Resistance |
| 695 ## - | |
| -- | Robustness |
| 695 ## - | |
| -- | Semiconductor device modeling |
| 695 ## - | |
| -- | Stress |
| 695 ## - | |
| -- | System-on-a-chip |
| 695 ## - | |
| -- | Testing |
| 695 ## - | |
| -- | Thyristors |
| 695 ## - | |
| -- | Time frequency analysis |
| 695 ## - | |
| -- | Transient analysis |
| 695 ## - | |
| -- | Voltage control |
| 695 ## - | |
| -- | Voltage measurement |
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