SiP-system in package design and simulation : (Record no. 68919)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 04136cam a2200649 i 4500 |
| 001 - CONTROL NUMBER | |
| control field | ocn974912967 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20220711203431.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 170307s2017 si ob 001 0 eng |
| 019 ## - | |
| -- | 994093602 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9781119046011 |
| -- | (Adobe PDF) |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 1119046017 |
| -- | (Adobe PDF) |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9781119046004 |
| -- | (ePub) |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 1119046009 |
| -- | (ePub) |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9781119045991 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 1119045991 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| -- | (cloth) |
| 029 1# - (OCLC) | |
| OCLC library identifier | AU@ |
| System control number | 000059700878 |
| 029 1# - (OCLC) | |
| OCLC library identifier | CHBIS |
| System control number | 011150703 |
| 029 1# - (OCLC) | |
| OCLC library identifier | CHNEW |
| System control number | 000964866 |
| 029 1# - (OCLC) | |
| OCLC library identifier | CHVBK |
| System control number | 495227315 |
| 029 1# - (OCLC) | |
| OCLC library identifier | CHVBK |
| System control number | 508821649 |
| 029 1# - (OCLC) | |
| OCLC library identifier | DEBSZ |
| System control number | 493821120 |
| 029 1# - (OCLC) | |
| OCLC library identifier | GBVCP |
| System control number | 1014965802 |
| 082 00 - CLASSIFICATION NUMBER | |
| Call Number | 621.3815 |
| 100 1# - AUTHOR NAME | |
| Author | Li, Suny, |
| 245 10 - TITLE STATEMENT | |
| Title | SiP-system in package design and simulation : |
| Sub Title | Mentor EE Flow Advanced Design Guide / |
| 300 ## - PHYSICAL DESCRIPTION | |
| Number of Pages | 1 online resource |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Remark 2 | SiP design and simulation platform -- Basic knowledge of package -- SiP production process -- New package technologies -- SiP design and simulation flow -- Central library -- Schematic input -- Multi-board project management and schematic concurrent design -- Layout creation and setting -- Constraint rules management -- Wire bond design -- Cavity and chip stack design -- FlipChip and RDL design -- Route and plane -- Embedded passives design -- RF circuit design -- Layout concurrent design -- 3D real-time DRC -- Design review -- Manufacture data output -- SiP simulation technology. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc | An advanced reference documenting, in detail, every step of a real System-in-Package (SiP) design flow Written by an engineer at the leading edge of SiP design and implementation, this book demonstrates how to design SiPs using Mentor EE Flow. Key topics covered include wire bonding, die stacks, cavity, flip chip and RDL (redistribution layer), Embedded Passive, RF design, concurrent design, Xtreme design, 3D real-time DRC (design rule checking), and SiP manufacture. Extensively illustrated throughout, System in Package Design and Simulation covers an array of issues of vital concern for SiP design and fabrication electronics engineers, as well as SiP users, including: -Cavity and sacked dies design -FlipChip and RDL design -Routing and coppering -3D Real-Time DRC check -SiP simulation technology -Mentor SiP Design and Simulation Platform Designed to function equally well as a reference, tutorial, and self-study, System in Package Design and Simulation is an indispensable working resource for every SiP designer, especially those who use Mentor design tools. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| General subdivision | Design and construction. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| General subdivision | Design and construction. |
| 650 #7 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| General subdivision | Mechanical. |
| 650 #7 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| General subdivision | Design and construction. |
| 650 #7 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| General subdivision | Design and construction. |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | https://doi.org/10.1002/9781119045991 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | eBooks |
| 264 #1 - | |
| -- | Singapore ; |
| -- | Hoboken, NJ : |
| -- | Publishing House of Electronics Industry/Wiley, |
| -- | 2017. |
| 336 ## - | |
| -- | text |
| -- | txt |
| -- | rdacontent |
| 337 ## - | |
| -- | computer |
| -- | c |
| -- | rdamedia |
| 338 ## - | |
| -- | online resource |
| -- | cr |
| -- | rdacarrier |
| 588 0# - | |
| -- | Print version record and CIP data provided by publisher. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Integrated circuits |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Multichip modules (Microelectronics) |
| 650 #7 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | TECHNOLOGY & ENGINEERING |
| 650 #7 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Integrated circuits |
| -- | (OCoLC)fst00975545 |
| 650 #7 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Multichip modules (Microelectronics) |
| -- | (OCoLC)fst01028809 |
| 994 ## - | |
| -- | 92 |
| -- | DG1 |
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