CAD of circuits and integrated systems (Record no. 69300)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 04619cam a2200505Ia 4500 |
| 001 - CONTROL NUMBER | |
| control field | on1178633317 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20220711203609.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 200725s2020 enk ob 001 0 eng d |
| 019 ## - | |
| -- | 1176326200 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9781119751595 |
| -- | (electronic bk. : oBooks) |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 1119751594 |
| -- | (electronic bk. : oBooks) |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9781119751571 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 1119751578 |
| 082 04 - CLASSIFICATION NUMBER | |
| Call Number | 621.3815 |
| 100 1# - AUTHOR NAME | |
| Author | Mahdoum, Ali. |
| 245 10 - TITLE STATEMENT | |
| Title | CAD of circuits and integrated systems |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
| Place of publication | London : |
| Publisher | ISTE Ltd. ; |
| Place of publication | Hoboken : |
| Publisher | Wiley, |
| Year of publication | 2020. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Number of Pages | 1 online resource (293 p.) |
| 500 ## - GENERAL NOTE | |
| Remark 1 | Description based upon print version of record. |
| 505 8# - FORMATTED CONTENTS NOTE | |
| Remark 2 | 1.3. Heuristics and metaheuristics -- 1.3.1. Definitions -- 1.3.2. Graph theory -- 1.3.3. Branch and bound technique -- 1.3.4. Tabu search technique -- 1.3.5. Simulated annealing technique -- 1.3.6. Genetic and evolutionary algorithms -- 1.4. Conclusion -- 2. Basic Notions on the Design of Digital Circuits and Systems -- 2.1. Introduction -- 2.2. History of VLSI circuit design -- 2.2.1. Prediffused circuit -- 2.2.2. Sea of gates -- 2.2.3. Field-programmable gate array -- FPGA -- 2.2.4. Elementary pre-characterized circuit (standard cells) -- 2.2.5. Full-custom circuit -- 2.2.6. Silicon compilation |
| 505 8# - FORMATTED CONTENTS NOTE | |
| Remark 2 | 2.3. System design level -- 2.3.1. Synthesis -- 2.3.2. Floorplanning -- 2.3.3. Analysis -- 2.3.4. Verification -- 2.4. Register transfer design level -- 2.4.1. Synthesis -- 2.4.2. Analysis -- 2.4.3. Verification -- 2.5. Module design level -- 2.5.1. Synthesis -- 2.5.2. Analysis -- 2.5.3. Verification -- 2.6. Gate design level -- 2.6.1. Synthesis -- 2.6.2. Analysis -- 2.6.3. Verification -- 2.7. Transistor level -- 2.7.1. NMOS and CMOS technologies -- 2.7.2. Theory of MOS transistor (current IDS) -- 2.7.3. Transfer characteristics of the inverter -- 2.7.4. Static analysis of the inverter |
| 505 8# - FORMATTED CONTENTS NOTE | |
| Remark 2 | 2.7.5. Threshold voltage of the inverter -- 2.7.6. Estimation of the rise and fall times of a capacitor -- 2.8. Interconnections -- 2.8.1. Synthesis of interconnections -- 2.8.2. Synthesis of networks-on-chip -- 2.9. Conclusion -- 3.Case Study: Application of Heuristics and Metaheuristics in the Design of Integrated Circuits and Systems -- 3.1. Introduction -- 3.2. System level -- 3.2.1. Synthesis of systems-on-chip (SoCs) with low energy consumption -- 3.2.2. Heuristic application to dynamic voltage and frequency scaling (DVFS) for the design of a real-time system subject to energy constraint |
| 505 8# - FORMATTED CONTENTS NOTE | |
| Remark 2 | 3.3. Register transfer level -- 3.3.1. Integer linear programming applied to the scheduling of operations of a data flow graph (DFG) -- 3.3.2. The scheduling of operations in a controlled data flow graph (considering the speed-power consumption tradeoff) -- 3.3.3. Efficient code assignment to the states of a finite state machine (aimed at reaching an effective control part in terms of surface, speed and power consumption) |
| 500 ## - GENERAL NOTE | |
| Remark 1 | 3.3.4. Synthesis of submicron transistors and interconnections for the design of high-performance (low-power) circuits subject to power (respectively time) and surface constraints |
| 590 ## - LOCAL NOTE (RLIN) | |
| Local note | John Wiley and Sons |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| General subdivision | Computer-aided design. |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | https://doi.org/10.1002/9781119751595 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | eBooks |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Integrated circuits |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Computational complexity. |
| 994 ## - | |
| -- | 92 |
| -- | DG1 |
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