EDA for IC system design, verification, and testing / (Record no. 71590)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 02813cam a2200349Ii 4500 |
| 001 - CONTROL NUMBER | |
| control field | 9781420007947 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 180706s2006 flua ob 001 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9781420007947 |
| -- | (e-book : PDF) |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9781315221700 |
| -- | (e-book) |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9781351828901 |
| -- | (e-book: Mobi) |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| -- | (hardback) |
| 082 04 - CLASSIFICATION NUMBER | |
| Call Number | 621.3815 |
| -- | E211 |
| 245 00 - TITLE STATEMENT | |
| Title | EDA for IC system design, verification, and testing / |
| 300 ## - PHYSICAL DESCRIPTION | |
| Number of Pages | 1 online resource (544 pages). |
| 490 0# - SERIES STATEMENT | |
| Series statement | Electronic design automation for integrated circuits handbook |
| 500 ## - GENERAL NOTE | |
| Remark 1 | Companion volume of: EDA for IC implementation, circuit design, and process technology. |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Remark 2 | chapter 1 Overview -- chapter 2 The Integrated Circuit Design Process and Electronic Design Automation -- chapter 3 Tools and Methodologies for System-Level Design -- chapter 4 System-Level Specification and Modeling Languages -- chapter 5 SoC Block-Based Design and IP Assembly -- chapter 6 Performance Evaluation Methods for Multiprocessor System-on-Chip Design -- chapter 7 System-Level Power Management -- chapter 8 Processor Modeling and Design Tools -- chapter 9 Embedded Software Modeling and Design -- chapter 10 Using Performance Metrics to Select Microprocessor Cores for IC Designs -- chapter 11 Parallelizing High-Level Synthesis: A Code Transformational Approach to High-Level Synthesis -- chapter 12 Cycle-Accurate System-Level Modeling and Performance Evaluation -- chapter 13 Micro-Architectural Power Estimation and Optimization -- chapter 14 Design Planning -- chapter 15 Design and Verification Languages -- chapter 16 Digital Simulation -- chapter 17 Using Transactional-Level Models in an SoC Design Flow -- chapter 18 Assertion-Based Verification -- chapter 19 Hardware Acceleration and Emulation -- chapter 20 Formal Property Verification -- chapter 21 Design-For-Test -- chapter 22 Automatic Test Pattern Generation -- chapter 23 Analog and Mixed Signal Test. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| General subdivision | Computer-aided design. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| General subdivision | Verification |
| -- | Data processing. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Lavagno, Luciano, |
| 700 1# - AUTHOR 2 | |
| Author 2 | Martin, Grant |
| 700 1# - AUTHOR 2 | |
| Author 2 | Scheffer, Louis Kossuth. |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | https://www.taylorfrancis.com/books/9781420007947 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | eBooks |
| 264 #1 - | |
| -- | Boca Raton, FL : |
| -- | CRC Taylor & Francis, |
| -- | 2006. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Integrated circuits |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Integrated circuits |
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