Advanced FPGA design : (Record no. 73669)
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| 000 -LEADER | |
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| fixed length control field | 09117nam a2201213 i 4500 |
| 001 - CONTROL NUMBER | |
| control field | 5201491 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20220712205543.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 071115t20152007njua ob 001 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9780470127896 |
| -- | electronic |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| -- | paper |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| -- | electronic |
| 082 04 - CLASSIFICATION NUMBER | |
| Call Number | 621.39/5 |
| 100 1# - AUTHOR NAME | |
| Author | Kilts, Steve, |
| 245 10 - TITLE STATEMENT | |
| Title | Advanced FPGA design : |
| Sub Title | architecture, implementation, and optimization / |
| 300 ## - PHYSICAL DESCRIPTION | |
| Number of Pages | 1 PDF (xv, 336 pages) : |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Remark 2 | Preface -- Acknowledgments -- Chapter 1. Architecting Speed -- High Throughput -- Low Latency -- Timing -- Add Register Layers -- Parallel Structures -- Flatten Logic Structures -- Register Balancing -- Reorder Paths -- Summary of Key Points -- Chapter 2. Architecting Area -- Rolling-up the Pipeline -- Control Based Logic Reuse -- Resource Sharing -- Impact of Reset on Area -- Resources without Reset -- Resources without Set -- Resources without Asynchronous Reset -- Resetting RAM -- Utilizing Set/Reset Flip-Flop Pins -- Summary of Key Points -- Chapter 3. Architecting Power -- Clock Gating -- Clock Skew -- Managing Skew -- Gated Domains -- Input Control -- Reducing the Voltage Supply -- Dual-Edge Triggered Flip-Flops -- Modifying Terminations -- Summary of Key Points -- Chapter 4. Example Design: The Advanced Encryption Standard -- AES Architectures -- Compact Architecture -- Partially Pipelined Architecture -- Fully Pipelined Architecture -- Performance versus Area -- Other Optimizations -- Chapter 5. High Level Design -- Abstract Design Techniques -- Graphical State Machines -- DSP Design -- Software/Hardware Co-Design -- Summary of Key Points -- Chapter 6. Clock Domains -- Crossing Clock Domains -- Metastability -- Solution 1: Phase Control -- Solution 2: Double-flopping -- Solution 3: FIFO Structure -- Partitioning Synchronizer Blocks -- Gated Clocks in ASIC Prototypes -- Clocks Module -- Gating Removal -- Summary of Key Points -- Chapter 7. Example Design: I2S versus SPDIF -- I2S -- Protocol -- Hardware Architecture -- Analysis -- SPDIF -- Protocol -- Hardware Architecture -- Analysis -- Chapter 8. Implementing Math Functions -- Hardware Division -- Multiply and Shift -- Iterative Division -- The Goldschmidt Method -- Taylor and Maclaurin Series Expansion -- The CORDIC Algorithm -- Summary of Key Points -- Chapter 9. Example Design: Floating Point Unit -- Floating Point Formats -- Pipelined Architecture. |
| 505 8# - FORMATTED CONTENTS NOTE | |
| Remark 2 | Verilog Implementation -- Resources and Performance -- Chapter 10. Reset Circuits -- Asynchronous versus Synchronous -- Problems with Fully Asynchronous Resets -- Fully Synchronized Resets -- Asynchronous Assertion, Synchronous Deassertion -- Mixing Reset Types -- Non-Resetable Flip-Flops -- Internally Generated Resets -- Multiple Clock Domains -- Summary of Key Points -- Chapter 11. Advanced Simulation -- Testbench Architecture -- Testbench Components -- Testbench Flow -- Main Thread -- Clocks and Resets -- Testcases -- System Stimulus -- Matlab -- Bus-functional Models -- Code Coverage -- Gate Level Simulations -- Toggle Coverage -- Run-Time Traps -- Timescale -- Glitch Rejection -- Combinatorial Delay Modeling -- Summary of Key Points -- Chapter 12. Coding for Synthesis -- Decision Trees -- Priority versus Parallel -- Full Conditions -- Multiple Control Branches -- Traps -- Blocking versus Nonblocking -- For Loops -- Combinatorial Loops -- Inferred Latches -- Functions -- Design Organization -- Partitioning -- Datapath versus Control -- Clock and Reset Structures -- Multiple Instantiations -- Parameterization -- Definitions -- Parameters -- Parameters in Verilog-2001 -- Summary of Key Points -- Chapter 13. Example Design: The Secure Hash Algorithm -- SHA-1 Architecture -- Implementation Results -- Chapter 14. Synthesis Optimization -- Speed versus Area -- Resource Sharing -- Pipelining, Retiming, and Register Balancing -- The Effect of Reset on Register Balancing -- Resynchronization Registers -- FSM Compilation -- Removal of Unreachable States -- Black Boxes -- Physical Synthesis -- Forward versus Back-Annotation -- Graph Based Physical Synthesis -- Summary of Key Points -- Chapter 15. Floorplanning -- Design Partitioning -- Critical Path Floorplanning -- Floorplanning Dangers -- Optimal Floorplanning -- Data Path -- High Fan-Out -- Device Structure -- Reusability -- Reducing Power Dissipation. |
| 505 8# - FORMATTED CONTENTS NOTE | |
| Remark 2 | Summary of Key Points -- Chapter 16. Place and Route Optimization -- Optimal Constraints -- Relationship between Placement and Routing -- Logic Replication -- Optimization across Hierarchy -- I/O Registers -- Pack Factor -- Mapping Logic into RAM -- Register Ordering -- Placement Seed -- Guided Place and Route -- Summary of Key Points -- Chapter 17. Example Design: Microprocessor -- SRC Architecture -- Synthesis Optimizations -- Speed versus Area -- Pipelining -- Physical Synthesis -- Floorplan Optimizations -- Partitioned Floorplan -- Critical Path Floorplan: Abstraction 1 -- Critical Path Floorplan: Abstraction 2 -- Chapter 18. Static Timing Analysis -- Standard Analysis -- Latches -- Asynchronous Circuits -- Combinatorial Feedback -- Event Driven Clocks -- Summary of Key Points -- Chapter 19. PCB Issues -- Power Supply -- Supply Requirements -- Regulation -- Decoupling Capacitors -- Concept -- Calculating Values -- Capacitor Placement -- Power Planes -- Modeling Signal Reflections -- Spice Simulations -- Configuration -- Debug -- Code Modifications -- FPGA Editor -- Placement -- Properties -- Routing -- ChipScope -- Identify -- Summary of Key Points -- Appendix A -- Appendix B -- Bibliography -- Index. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc | This book provides the advanced issues of FPGA design as the underlying theme of the work. In practice, an engineer typically needs to be mentored for several years before these principles are appropriately utilized. The topics that will be discussed in this book are essential to designing FPGA's beyond moderate complexity. The goal of the book is to present practical design techniques that are otherwise only available through mentorship and real-world experience. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| Subject | Field programmable gate arrays |
| General subdivision | Design and construction. |
| 856 42 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | https://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=5201491 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | eBooks |
| 264 #1 - | |
| -- | Hoboken, New Jersey : |
| -- | Wiley : |
| -- | c2007. |
| 336 ## - | |
| -- | text |
| -- | rdacontent |
| 337 ## - | |
| -- | electronic |
| -- | isbdmedia |
| 338 ## - | |
| -- | online resource |
| -- | rdacarrier |
| 588 ## - | |
| -- | Description based on PDF viewed 12/19/2015. |
| 695 ## - | |
| -- | Adders |
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| -- | Algorithm design and analysis |
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| -- | Analytical models |
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| -- | Approximation algorithms |
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| -- | Approximation methods |
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| -- | Automation |
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| -- | Bibliographies |
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| -- | Capacitors |
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| -- | Clocks |
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| -- | Computer architecture |
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| -- | Decision trees |
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| -- | Delay |
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| -- | Design automation |
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| -- | Digital signal processing |
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| -- | Encoding |
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| -- | Encryption |
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| -- | Field programmable gate arrays |
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| -- | Generators |
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| -- | Hardware |
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| -- | Hardware design languages |
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| -- | IEEE standards |
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| -- | Image edge detection |
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| -- | Indexes |
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| -- | Industries |
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| -- | Iterative algorithm |
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| -- | Iterative methods |
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| -- | Latches |
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| -- | Layout |
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| -- | Lead |
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| -- | Logic gates |
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| -- | Microprocessors |
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| -- | NIST |
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| -- | Niobium |
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| -- | Optimization |
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| -- | Performance evaluation |
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| -- | Pipeline processing |
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| -- | Pipelines |
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| -- | Power dissipation |
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| -- | Power supplies |
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| -- | Protocols |
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| -- | Radiation detectors |
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| -- | Rails |
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| -- | Read only memory |
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| -- | Receivers |
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| -- | Regions |
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| -- | Registers |
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| -- | Reliability engineering |
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| -- | Resource management |
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| -- | Routing |
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| -- | Schedules |
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| -- | Sections |
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| -- | Shift registers |
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| -- | Software |
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| -- | Synchronization |
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| -- | Threshold voltage |
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| -- | Throughput |
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| -- | Timing |
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| -- | Topology |
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| -- | Transient analysis |
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| -- | Voltage control |
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| -- | Wire |
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