Monolithic phase-locked loops and clock recovery circuits : (Record no. 73829)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 11124nam a2201957 i 4500 |
| 001 - CONTROL NUMBER | |
| control field | 5263221 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20220712205629.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 100317t20151996nyua ob 001 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9780470545331 |
| -- | electronic |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| -- | |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| -- | electronic |
| 082 04 - CLASSIFICATION NUMBER | |
| Call Number | 621.3815/364 |
| 245 00 - TITLE STATEMENT | |
| Title | Monolithic phase-locked loops and clock recovery circuits : |
| Sub Title | theory and design / |
| 300 ## - PHYSICAL DESCRIPTION | |
| Number of Pages | 1 PDF (ix, 498 pages) : |
| 500 ## - GENERAL NOTE | |
| Remark 1 | "A selected reprint volume." |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Remark 2 | Preface -- Design of Monolithic Phase-Locked Loops and Clock Recovery Circuits -- A Tutorial (B. Razavi) -- BASIC THEORY -- Theory of AFC Synchronization (W. Gruen) -- Color-Carrier Reference Phase Synchronization Accuracy in NTSC Color Television (D. Richman) -- Charge-Pump Phase-Locked Loops (F. Gardner) -- z-Domain Model for Discrete-Time PLLs (J. Hein & J. Scott) -- Analyze PLLs with Discrete Time Modeling (J. Kovacs) -- Properties of Frequency Difference Detectors (F. Gardner) -- Frequency Detectors for PLL Acquisition in Timing and Carrier Recovery (D. Messerschmitt) -- Analysis of Phase-Locked Timing Extraction Circuits for Pulse Code Transmission (E. Roza) -- Optimization of Phase-Locked Loop Performance in Data Recovery Systems (R. Co & J. Mulligan) -- Noise Properties of PLL Systems (V. Kroupa) -- PLL/DLL System Noise Analysis for Low Jitter Clock Synthesizer Design (B. Kim, et al.) -- Practical Approach Augurs PLL Noise in RF Synthesizers (M. O'Leary) -- The Effects of Noise in Oscillators (E. Hafner) -- A Simple Model of Feedback Oscillator Noise Spectrum (D. Leeson) -- Noise in Relaxation Oscillators (A. Abidi & R. Meyer) -- Analysis of Timing Jitter in CMOS Ring Oscillators (T. Weigandt, et al.) -- Analysis, Modeling, and Simulation of Phase Noise in Monolithic Voltage-Controlled Oscillators (B. Razavi) -- BUILDING BLOCKS -- Start-up and Frequency Stability in High-Frequency Oscillators (N. Nguyen & R. Meyer) -- MOS Oscillators with Multi-Decade Tuning Range and Gigahertz Maximum Speed (M. Banu) -- A Bipolar 1 GHz Multi-Decade Monolithic Variable-Frequency Oscillator (J. Wu) -- A Digital Phase and Frequency Sensitive Detector (J. Brown) -- A 3-State Phase Detector Can Improve Your Next PLL Design (C. Sharpe) -- GaAs Monolithic Phase/Frequency Discriminator (I. Shahriary, et al.) -- A New Phase-Locked Loop Timing Recovery Method for Digital Regenerators (J. Bellisio) -- A Phase-Locked Loop with Digital Frequency Comparator for Timing Signal Recovery (J. Afonso, et al.). |
| 505 8# - FORMATTED CONTENTS NOTE | |
| Remark 2 | Clock Recovery from Random Binary Signals (J. Alexander) -- A Si Bipolar Phase and Frequency Detector IC for Clock Extraction up to 8 Gb/s (A. Pottbacker, et al.) -- A Self-Correcting Clock Recovery Circuit (C. Hogge) -- MODELING AND SIMULATION -- An Integrated PLL Clock Generator for 275 MHz Graphic Displays (G. Gutierrez & D. DeSimone) -- The Macro Modeling of Phase-Locked Loopes for the SPICE Simulator (M. Sitkowski) -- Modeling and Simulation of an Analog Charge Pump Phase-Locked Loop (S. Can & Y. Sahinkaya) -- Mixed-Mode Simulation of Phase-Locked Loops (B. Antao, et al.) -- Behavioral Representation for VCO and Detectors in Phase-Lock Systems (E. Liu & A. Sangiovanni-Vincentelli) -- Behavioral Simulation Techniques for Phase/Delay-Locked Systems (A. Demir, et al.) -- PHASE-LOCKED LOOPS -- A Monolithic Phase-Locked Loop with Detection Processor (E. Murthi) -- A 200-MHz CMOS Phase-Locked Loop with Dual Phase Detectors (K. Ware, et al.) -- High-Frequency Phase-Locked Loops in Monolithic Bipolar Technology (M. Soyuer & R. Meyer) -- A 6-GHz Integrated Phase-Locked Loop Using AlGaAs/GaAs Heterojunction Bipolar Transistors (A. Buchwald, et al.) -- A 6-GHz 60-mW BiCMOS Phase-Locked Loop with 2-V Supply (B. Razavi & J. Sung) -- Design of PLL-Based Clock Generation Circuits (D. Jeong) -- A Variable Delay Line PLL for CPU-Coprocessor Synchronization (M. Johnson & E. Hudson) -- A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors (I. Young, et al.) -- A Wide-Bandwidth Low-Voltage PLL for PowerPC Microprocessors (J. Alvarez, et al.) -- A 30-128 MHz Frequency Synthesizer Standard Cell (R. Bitting & W. Repasky) -- Cell-Based Fully Integrated CMOS Frequency Synthesizers (D. Mijuskovic, et al.) -- Fully-Integrated CMOS Phase-Locked Loop with 15 to 240 MHz Locking Range and ?50 psec Jitter (I. Novof, et al.) -- PLL Design for a 500 MB/s Interface (M. Horowitz, et al.) -- CLOCK AND DATA RECOVERY CIRCUITS -- An Analog PLL-Based Clock and Data Recovery Circuit with High Input Jitter Tolerance (S. Sun). |
| 505 8# - FORMATTED CONTENTS NOTE | |
| Remark 2 | A 30-MHz Hybrid Analog/Digital Clock Recovery Circuit in 2-aL1/4m CMOS (B. Kim, et al.) -- A BiCMOS PLL-Based Data Separator Circuit with High Stability and Accuracy (S. Miyazawa, et al.) -- A Versatile Clock Recovery Architecture and Monlithic Implementation (L. De Vito) -- A 155-MHz Clock Recovery Delay- and Phase-Locked Loop (T. Lee & J. Bulzacchelli) -- A Monolithic 156 Mb/s Clock and Data Recovery PLL Circuit using the Sample- and-Hold Technique (N. Ishihara & Y. Akazawa) -- A Monolithic 480 Mb/s Parallel AGC/Decision/Clock Recovery Circuit in 1.2-aL1/4m CMOS (T. Hu & P. Gray) -- A Monolithic 622 Mb/sec Clock Extraction and Data Retiming Circuit (B. Lai & R. Walker) -- A 660 Mb/s CMOS Clock Recovery Circuit with Instantaneous Locking for NRZ Data and Burst-Mode Transmission (M. Banu & A. Dunlop) -- A Monolithic 2.3-Gb/s 100-mW Clock and Data Recovery Circuit in Silicon Bipolar Technology (M. Soyuer) -- A 50 MHz Phase- and Frequency-Locked Loop (R. Cordell, et al.) -- NMOS ICs for Clock and Data Regeneration in Gigabit-per-Second Optical-Fiber Receivers (S. Enam & A. Abidi) -- A PLL-Based 2.5-Gb/s Clock and Data Regenerator IC (H. Ransijn & P. O'Connor) -- A 2.5-Gb/sec 15-mW BiCMOS Clock Recovery Circuit (B. Razavi & J. Sung) -- An 8 GHz Silicon Bipolar Clock Recovery and Data Regenerator IC (A. Pottbacker & U. Langmann) -- Author Index -- Subject Index -- Editor's Biography. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| Subject | Phase-locked loops |
| General subdivision | Design and construction. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| Subject | Timing circuits |
| General subdivision | Design and construction. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| Subject | Integrated circuits |
| General subdivision | Design and construction. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Razavi, Behzad. |
| 856 42 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | https://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=5263221 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | eBooks |
| 264 #1 - | |
| -- | New York : |
| -- | IEEE Press, |
| -- | c1996. |
| 264 #2 - | |
| -- | [Piscataqay, New Jersey] : |
| -- | IEEE Xplore, |
| -- | [1996] |
| 336 ## - | |
| -- | text |
| -- | rdacontent |
| 337 ## - | |
| -- | electronic |
| -- | isbdmedia |
| 338 ## - | |
| -- | online resource |
| -- | rdacarrier |
| 588 ## - | |
| -- | Description based on PDF viewed 12/21/2015. |
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| -- | Accuracy |
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| -- | Active circuits |
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| -- | Approximation methods |
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| -- | Band pass filters |
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| -- | Bandwidth |
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| -- | Baseband |
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| -- | BiCMOS integrated circuits |
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| -- | Biographies |
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| -- | CMOS integrated circuits |
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| -- | Capacitors |
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| -- | Central Processing Unit |
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| -- | Charge pumps |
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| -- | Clocks |
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| -- | Color |
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| -- | Combinational circuits |
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| -- | Computational modeling |
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| -- | Crystals |
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| -- | Data mining |
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| -- | Data models |
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| -- | Decoding |
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| -- | Delay |
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| -- | Delay lines |
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| -- | Detectors |
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| -- | Distortion |
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| -- | Driver circuits |
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| -- | Equations |
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| -- | Filtering |
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| -- | Filtering theory |
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| -- | Flip-flops |
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| -- | Frequency control |
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| -- | Frequency locked loops |
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| -- | Frequency measurement |
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| -- | Frequency modulation |
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| -- | Frequency shift keying |
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| -- | Frequency synthesizers |
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| -- | Gain |
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| -- | Gallium arsenide |
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| -- | Generators |
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| -- | Harmonic analysis |
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| -- | Heterojunction bipolar transistors |
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| -- | Indexes |
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| -- | Inductance |
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| -- | Integrated circuit modeling |
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| -- | Inverters |
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| -- | Mixers |
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| -- | Noise |
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| -- | Noise measurement |
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| -- | Numerical models |
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| -- | Optical signal processing |
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| -- | Oscillators |
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| -- | Particle separators |
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| -- | Passive filters |
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| -- | Phase frequency detector |
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| -- | Phase locked loops |
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| -- | Phase noise |
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| -- | Phase shift keying |
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| -- | Phase shifters |
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| -- | Pixel |
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| -- | Receivers |
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| -- | Registers |
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| -- | Reliability |
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| -- | Ring oscillators |
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| -- | SONET |
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| -- | Silicon |
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| -- | Stability criteria |
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| -- | Steady-state |
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| -- | Strontium |
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| -- | Switches |
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| -- | Synchronization |
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| -- | Synthesizers |
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| -- | Temperature measurement |
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| -- | Time frequency analysis |
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| -- | Timing |
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| -- | Timing jitter |
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| -- | Tracking loops |
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| -- | Transfer functions |
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| -- | Transistors |
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| -- | Tuning |
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| -- | Varactors |
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| -- | Voltage control |
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| -- | Voltage-controlled oscillators |
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| -- | Wideband |
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