Hardware Architectures for Post-Quantum Digital Signature Schemes (Record no. 75676)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 03514nam a22005895i 4500 |
| 001 - CONTROL NUMBER | |
| control field | 978-3-030-57682-0 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20220801213844.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 201027s2021 sz | s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9783030576820 |
| -- | 978-3-030-57682-0 |
| 082 04 - CLASSIFICATION NUMBER | |
| Call Number | 621.3815 |
| 100 1# - AUTHOR NAME | |
| Author | Soni, Deepraj. |
| 245 10 - TITLE STATEMENT | |
| Title | Hardware Architectures for Post-Quantum Digital Signature Schemes |
| 250 ## - EDITION STATEMENT | |
| Edition statement | 1st ed. 2021. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Number of Pages | XXII, 170 p. 68 illus., 66 illus. in color. |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Remark 2 | Introduction -- qTESLA -- CRYSTALS –Dilithium -- MQDSS -- SPHINCS -- Luov -- Falcon -- Picnic -- GeMSS -- Power, Performance, Area, and Security (PPAS) Comparison of the PQC Algorithms -- Conclusions. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc | This book explores C-based design, implementation, and analysis of post-quantum cryptography (PQC) algorithms for signature generation and verification. The authors investigate NIST round 2 PQC algorithms for signature generation and signature verification from a hardware implementation perspective, especially focusing on C-based design, power-performance-area-security (PPAS) trade-offs and design flows targeting FPGAs and ASICs. Describes a comprehensive set of synthesizable c code base as well as the hardware implementations for the different types of PQC algorithms including lattice-based, code-based, and multivariate-based; Demonstrates the hardware (FPGA and ASIC) and hardware-software optimizations and trade-offs of the NIST round 2 signature-based PQC algorithms; Enables designers to build hardware implementations that are resilient to a variety of side-channels. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Basu, Kanad. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Nabeel, Mohammed. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Aaraj, Najwa. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Manzano, Marc. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Karri, Ramesh. |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | https://doi.org/10.1007/978-3-030-57682-0 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | eBooks |
| 264 #1 - | |
| -- | Cham : |
| -- | Springer International Publishing : |
| -- | Imprint: Springer, |
| -- | 2021. |
| 336 ## - | |
| -- | text |
| -- | txt |
| -- | rdacontent |
| 337 ## - | |
| -- | computer |
| -- | c |
| -- | rdamedia |
| 338 ## - | |
| -- | online resource |
| -- | cr |
| -- | rdacarrier |
| 347 ## - | |
| -- | text file |
| -- | |
| -- | rda |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Electronic circuits. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Cooperating objects (Computer systems). |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Microprocessors. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Computer architecture. |
| 650 14 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Electronic Circuits and Systems. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Cyber-Physical Systems. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Processor Architectures. |
| 912 ## - | |
| -- | ZDB-2-ENG |
| 912 ## - | |
| -- | ZDB-2-SXE |
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