Mitigating Process Variability and Soft Errors at Circuit-Level for FinFETs (Record no. 76378)

000 -LEADER
fixed length control field 04724nam a22005535i 4500
001 - CONTROL NUMBER
control field 978-3-030-68368-9
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20220801214451.0
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 210310s2021 sz | s |||| 0|eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
ISBN 9783030683689
-- 978-3-030-68368-9
082 04 - CLASSIFICATION NUMBER
Call Number 621.3815
100 1# - AUTHOR NAME
Author Zimpeck, Alexandra.
245 10 - TITLE STATEMENT
Title Mitigating Process Variability and Soft Errors at Circuit-Level for FinFETs
250 ## - EDITION STATEMENT
Edition statement 1st ed. 2021.
300 ## - PHYSICAL DESCRIPTION
Number of Pages XIII, 131 p. 89 illus., 86 illus. in color.
505 0# - FORMATTED CONTENTS NOTE
Remark 2 Chapter 1. Introduction -- Chapter 2. FinFET Technology -- Chapter 3. Reliability Challenges in FinFETs -- Chapter 4. Circuit-Level Mitigation Approaches -- Chapter 5. Evaluation Methodology -- Chapter 6. Process Variability Mitigation -- Chapter 7. Soft Error Mitigation -- Chapter 8. General Trade-offs -- Chapter 9. Final Remarks.
520 ## - SUMMARY, ETC.
Summary, etc This book evaluates the influence of process variations (e.g. work-function fluctuations) and radiation-induced soft errors in a set of logic cells using FinFET technology, considering the 7nm technological node as a case study. Moreover, for accurate soft error estimation, the authors adopt a radiation event generator tool (MUSCA SEP3), which deals both with layout features and electrical properties of devices. The authors also explore four circuit-level techniques (e.g. transistor reordering, decoupling cells, Schmitt Trigger, and sleep transistor) as alternatives to attenuate the unwanted effects on FinFET logic cells. This book also evaluates the mitigation tendency when different levels of process variation, transistor sizing, and radiation particle characteristics are applied in the design. An overall comparison of all methods addressed by this work is provided allowing to trace a trade-off between the reliability gains and the design penalties of each approach regarding the area, performance, power consumption, single event transient (SET) pulse width, and SET cross-section. Explains how to measure the influence of process variability (e.g. work-function fluctuations) and radiation-induced soft errors in FinFET logic cells; Enables designers to improve the robustness of FinFET integrated circuits without focusing on manufacturing adjustments; Discusses the benefits and downsides of using circuit-level approaches such as transistor reordering, decoupling cells, Schmitt Trigger, and sleep transistor for mitigating the impact of process variability and soft errors; Evaluates the techniques described in the context of different test scenarios: distinct levels of process variations, transistor sizing, and different radiation features; Helps readers identify the best circuit design considering the target application and design requirements like area constraints or power/delay limitations.
700 1# - AUTHOR 2
Author 2 Meinhardt, Cristina.
700 1# - AUTHOR 2
Author 2 Artola, Laurent.
700 1# - AUTHOR 2
Author 2 Reis, Ricardo.
856 40 - ELECTRONIC LOCATION AND ACCESS
Uniform Resource Identifier https://doi.org/10.1007/978-3-030-68368-9
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type eBooks
100 1# - AUTHOR NAME
-- (orcid)0000-0002-3583-1002
-- https://orcid.org/0000-0002-3583-1002
264 #1 -
-- Cham :
-- Springer International Publishing :
-- Imprint: Springer,
-- 2021.
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-- text
-- txt
-- rdacontent
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-- computer
-- c
-- rdamedia
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-- online resource
-- cr
-- rdacarrier
347 ## -
-- text file
-- PDF
-- rda
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Electronic circuits.
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Electronic circuit design.
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Solid state physics.
650 14 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Electronic Circuits and Systems.
650 24 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Electronics Design and Verification.
650 24 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Electronic Devices.
700 1# - AUTHOR 2
-- (orcid)0000-0003-1088-1000
-- https://orcid.org/0000-0003-1088-1000
700 1# - AUTHOR 2
-- (orcid)0000-0003-0730-7518
-- https://orcid.org/0000-0003-0730-7518
700 1# - AUTHOR 2
-- (orcid)0000-0001-5781-5858
-- https://orcid.org/0000-0001-5781-5858
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-- ZDB-2-ENG
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-- ZDB-2-SXE

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