FPGA-BASED Hardware Accelerators (Record no. 77811)
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fixed length control field | 03925nam a22005295i 4500 |
001 - CONTROL NUMBER | |
control field | 978-3-030-20721-2 |
005 - DATE AND TIME OF LATEST TRANSACTION | |
control field | 20220801215733.0 |
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
fixed length control field | 190530s2019 sz | s |||| 0|eng d |
020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
ISBN | 9783030207212 |
-- | 978-3-030-20721-2 |
082 04 - CLASSIFICATION NUMBER | |
Call Number | 621.3815 |
100 1# - AUTHOR NAME | |
Author | Skliarova, Iouliia. |
245 10 - TITLE STATEMENT | |
Title | FPGA-BASED Hardware Accelerators |
250 ## - EDITION STATEMENT | |
Edition statement | 1st ed. 2019. |
300 ## - PHYSICAL DESCRIPTION | |
Number of Pages | XVI, 245 p. |
490 1# - SERIES STATEMENT | |
Series statement | Lecture Notes in Electrical Engineering, |
505 0# - FORMATTED CONTENTS NOTE | |
Remark 2 | Reconfigurable devices and design tools -- Architectures of FPGA-based hardware accelerators and design techniques -- Hardware accelerators for data search -- Hardware accelerators for data sort -- FPGA-based hardware accelerators for selected computational problems -- Hardware/software co-design. |
520 ## - SUMMARY, ETC. | |
Summary, etc | This book suggests and describes a number of fast parallel circuits for data/vector processing using FPGA-based hardware accelerators. Three primary areas are covered: searching, sorting, and counting in combinational and iterative networks. These include the application of traditional structures that rely on comparators/swappers as well as alternative networks with a variety of core elements such as adders, logical gates, and look-up tables. The iterative technique discussed in the book enables the sequential reuse of relatively large combinational blocks that execute many parallel operations with small propagation delays. For each type of network discussed, the main focus is on the step-by-step development of the architectures proposed from initial concepts to synthesizable hardware description language specifications. Each type of network is taken through several stages, including modeling the desired functionality in software, the retrieval and automatic conversion of key functions, leading to specifications for optimized hardware modules. The resulting specifications are then synthesized, implemented, and tested in FPGAs using commercial design environments and prototyping boards. The methods proposed can be used in a range of data processing applications, including traditional sorting, the extraction of maximum and minimum subsets from large data sets, communication-time data processing, finding frequently occurring items in a set, and Hamming weight/distance counters/comparators. The book is intended to be a valuable support material for university and industrial engineering courses that involve FPGA-based circuit and system design. |
700 1# - AUTHOR 2 | |
Author 2 | Sklyarov, Valery. |
856 40 - ELECTRONIC LOCATION AND ACCESS | |
Uniform Resource Identifier | https://doi.org/10.1007/978-3-030-20721-2 |
942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
Koha item type | eBooks |
264 #1 - | |
-- | Cham : |
-- | Springer International Publishing : |
-- | Imprint: Springer, |
-- | 2019. |
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-- | text |
-- | txt |
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-- | computer |
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-- | rdamedia |
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-- | online resource |
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347 ## - | |
-- | text file |
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-- | rda |
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
-- | Electronic circuits. |
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
-- | Computational intelligence. |
650 14 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
-- | Electronic Circuits and Systems. |
650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
-- | Computational Intelligence. |
830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE | |
-- | 1876-1119 ; |
912 ## - | |
-- | ZDB-2-ENG |
912 ## - | |
-- | ZDB-2-SXE |
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