Design for Testability, Debug and Reliability (Record no. 78265)

000 -LEADER
fixed length control field 03947nam a22005415i 4500
001 - CONTROL NUMBER
control field 978-3-030-69209-4
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20220801220145.0
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 210419s2021 sz | s |||| 0|eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
ISBN 9783030692094
-- 978-3-030-69209-4
082 04 - CLASSIFICATION NUMBER
Call Number 006.22
100 1# - AUTHOR NAME
Author Huhn, Sebastian.
245 10 - TITLE STATEMENT
Title Design for Testability, Debug and Reliability
Sub Title Next Generation Measures Using Formal Techniques /
250 ## - EDITION STATEMENT
Edition statement 1st ed. 2021.
300 ## - PHYSICAL DESCRIPTION
Number of Pages XXI, 164 p. 47 illus., 25 illus. in color.
505 0# - FORMATTED CONTENTS NOTE
Remark 2 Introduction -- Integrated Circuits -- Formal Techniques -- Embedded Compression Architecture for Test Access Ports -- Optimization SAT-based Retargeting for Embedded Compression -- Reconfigurable TAP Controllers with Embedded Compression -- Embedded Multichannel Test Compression for Low-Pin Count Test -- Enhanced Reliability using Formal Techniques -- Conclusion and Outlook.
520 ## - SUMMARY, ETC.
Summary, etc This book introduces several novel approaches to pave the way for the next generation of integrated circuits, which can be successfully and reliably integrated, even in safety-critical applications. The authors describe new measures to address the rising challenges in the field of design for testability, debug, and reliability, as strictly required for state-of-the-art circuit designs. In particular, this book combines formal techniques, such as the Satisfiability (SAT) problem and the Bounded Model Checking (BMC), to address the arising challenges concerning the increase in test data volume, as well as test application time and the required reliability. All methods are discussed in detail and evaluated extensively, while considering industry-relevant benchmark candidates. All measures have been integrated into a common framework, which implements standardized software/hardware interfaces. Provides readers with a combination of a comprehensive set of formal techniques covering and enhancing different aspects of the state-of-the-art design and test flow for ICs; Introduces newly developed heuristic, formal optimization-based and partition-based retargeting techniques and integrates them into a common framework; Describes fully compliant (with respect to industrial de-facto standard) measures to enhance the DFT, DFD and DFR capabilities while supporting standardized data exchange formats; Includes new measures to tackle shortcomings of existing state-of-the-art methods, including zero-defect enforcing safety-critical applications.
700 1# - AUTHOR 2
Author 2 Drechsler, Rolf.
856 40 - ELECTRONIC LOCATION AND ACCESS
Uniform Resource Identifier https://doi.org/10.1007/978-3-030-69209-4
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type eBooks
264 #1 -
-- Cham :
-- Springer International Publishing :
-- Imprint: Springer,
-- 2021.
336 ## -
-- text
-- txt
-- rdacontent
337 ## -
-- computer
-- c
-- rdamedia
338 ## -
-- online resource
-- cr
-- rdacarrier
347 ## -
-- text file
-- PDF
-- rda
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Embedded computer systems.
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Electronic circuit design.
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Microprocessors.
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Computer architecture.
650 14 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Embedded Systems.
650 24 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Electronics Design and Verification.
650 24 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Processor Architectures.
912 ## -
-- ZDB-2-ENG
912 ## -
-- ZDB-2-SXE

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