Electromigration Inside Logic Cells (Record no. 78879)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 03324nam a22005295i 4500 |
| 001 - CONTROL NUMBER | |
| control field | 978-3-319-48899-8 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20220801220731.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 161130s2017 sz | s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9783319488998 |
| -- | 978-3-319-48899-8 |
| 082 04 - CLASSIFICATION NUMBER | |
| Call Number | 621.3815 |
| 100 1# - AUTHOR NAME | |
| Author | Posser, Gracieli. |
| 245 10 - TITLE STATEMENT | |
| Title | Electromigration Inside Logic Cells |
| Sub Title | Modeling, Analyzing and Mitigating Signal Electromigration in NanoCMOS / |
| 250 ## - EDITION STATEMENT | |
| Edition statement | 1st ed. 2017. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Number of Pages | XX, 118 p. 72 illus., 69 illus. in color. |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Remark 2 | Chapter 1. Introduction -- Chapter 2. State of the Art -- Chapter 3. Modeling Cell-internal EM -- Chapter 4. Current Calculation -- Chapter 5. Experimental Setup -- Chapter 6.Results -- Chapter 7. Analyzing the Electromigration Effects on Different Metal Layers -- Chapter 8. Conclusions. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc | This book describes new and effective methodologies for modeling, analyzing and mitigating cell-internal signal electromigration in nanoCMOS, with significant circuit lifetime improvements and no impact on performance, area and power. The authors are the first to analyze and propose a solution for the electromigration effects inside logic cells of a circuit. They show in this book that an interconnect inside a cell can fail reducing considerably the circuit lifetime and they demonstrate a methodology to optimize the lifetime of circuits, by placing the output, Vdd and Vss pin of the cells in the less critical regions, where the electromigration effects are reduced. Readers will be enabled to apply this methodology only for the critical cells in the circuit, avoiding impact in the circuit delay, area and performance, thus increasing the lifetime of the circuit without loss in other characteristics. . |
| 700 1# - AUTHOR 2 | |
| Author 2 | Sapatnekar, Sachin S. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Reis, Ricardo. |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | https://doi.org/10.1007/978-3-319-48899-8 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | eBooks |
| 264 #1 - | |
| -- | Cham : |
| -- | Springer International Publishing : |
| -- | Imprint: Springer, |
| -- | 2017. |
| 336 ## - | |
| -- | text |
| -- | txt |
| -- | rdacontent |
| 337 ## - | |
| -- | computer |
| -- | c |
| -- | rdamedia |
| 338 ## - | |
| -- | online resource |
| -- | cr |
| -- | rdacarrier |
| 347 ## - | |
| -- | text file |
| -- | |
| -- | rda |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Electronic circuits. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Microprocessors. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Computer architecture. |
| 650 14 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Electronic Circuits and Systems. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Processor Architectures. |
| 700 1# - AUTHOR 2 | |
| -- | (orcid)0000-0001-5781-5858 |
| -- | https://orcid.org/0000-0001-5781-5858 |
| 912 ## - | |
| -- | ZDB-2-ENG |
| 912 ## - | |
| -- | ZDB-2-SXE |
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