Heterogeneous Reconfigurable Processors for Real-Time Baseband Processing (Record no. 80033)

000 -LEADER
fixed length control field 03702nam a22005415i 4500
001 - CONTROL NUMBER
control field 978-3-319-24004-6
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20220801221753.0
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 160118s2016 sz | s |||| 0|eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
ISBN 9783319240046
-- 978-3-319-24004-6
082 04 - CLASSIFICATION NUMBER
Call Number 621.3815
100 1# - AUTHOR NAME
Author Zhang, Chenxin.
245 10 - TITLE STATEMENT
Title Heterogeneous Reconfigurable Processors for Real-Time Baseband Processing
Sub Title From Algorithm to Architecture /
250 ## - EDITION STATEMENT
Edition statement 1st ed. 2016.
300 ## - PHYSICAL DESCRIPTION
Number of Pages XIV, 195 p. 81 illus., 29 illus. in color.
505 0# - FORMATTED CONTENTS NOTE
Remark 2 Introduction -- Digital Hardware Platforms -- Digital Baseband Processing -- The Reconfigurable Cell Array -- Multi-standard Digital Front-End Processing -- Multi-task MIMO Signal Processing -- Future Multi-user MIMO systems – A Discussion -- Conclusion.-.
520 ## - SUMMARY, ETC.
Summary, etc This book focuses on domain-specific heterogeneous reconfigurable architectures, demonstrating for readers a computing platform which is flexible enough to support multiple standards, multiple modes, and multiple algorithms. The content is multi-disciplinary, covering areas of wireless communication, computing architecture, and circuit design. The platform described provides real-time processing capability with reasonable implementation cost, achieving balanced trade-offs among flexibility, performance, and hardware costs. The authors discuss efficient design methods for wireless communication processing platforms, from both an algorithm and architecture design perspective. Coverage also includes computing platforms for different wireless technologies and standards, including MIMO, OFDM, Massive MIMO, DVB, WLAN, LTE/LTE-A, and 5G. •Discusses reconfigurable architectures, including hardware building blocks such as processing elements, memory sub-systems, Network-on-Chip (NoC), and dynamic hardware reconfiguration; •Describes a unique design and optimization methodology, applied to different areas and levels, including communication theory, hardware implementation, and software support; •Demonstrates design trade-offs during different development phases and enables readers to apply similar techniques to various applications.
700 1# - AUTHOR 2
Author 2 Liu, Liang.
700 1# - AUTHOR 2
Author 2 Öwall, Viktor.
856 40 - ELECTRONIC LOCATION AND ACCESS
Uniform Resource Identifier https://doi.org/10.1007/978-3-319-24004-6
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type eBooks
264 #1 -
-- Cham :
-- Springer International Publishing :
-- Imprint: Springer,
-- 2016.
336 ## -
-- text
-- txt
-- rdacontent
337 ## -
-- computer
-- c
-- rdamedia
338 ## -
-- online resource
-- cr
-- rdacarrier
347 ## -
-- text file
-- PDF
-- rda
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Electronic circuits.
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Microprocessors.
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Computer architecture.
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Electronics.
650 14 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Electronic Circuits and Systems.
650 24 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Processor Architectures.
650 24 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Electronics and Microelectronics, Instrumentation.
912 ## -
-- ZDB-2-ENG
912 ## -
-- ZDB-2-SXE

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