Analog Integrated Circuit Design Automation (Record no. 80382)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 03670nam a22005535i 4500 |
| 001 - CONTROL NUMBER | |
| control field | 978-3-319-34060-9 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20220801222102.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 160720s2017 sz | s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9783319340609 |
| -- | 978-3-319-34060-9 |
| 082 04 - CLASSIFICATION NUMBER | |
| Call Number | 621.3815 |
| 100 1# - AUTHOR NAME | |
| Author | Martins, Ricardo. |
| 245 10 - TITLE STATEMENT | |
| Title | Analog Integrated Circuit Design Automation |
| Sub Title | Placement, Routing and Parasitic Extraction Techniques / |
| 250 ## - EDITION STATEMENT | |
| Edition statement | 1st ed. 2017. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Number of Pages | XVI, 207 p. 108 illus., 79 illus. in color. |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Remark 2 | 1 Introduction -- 2 State-of-the-Art on Analog Layout Automation -- 3 AIDA-L: Architecture and Integration -- 4 Template-based Placer -- 5 Optimization-based Placer -- 6 Fully-Automatic Router -- 7 Empirical-based Parasitic Extractor -- 8 Experimental Results -- 9 Conclusions and Future Work. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc | This book introduces readers to a variety of tools for analog layout design automation. After discussing the placement and routing problem in electronic design automation (EDA), the authors overview a variety of automatic layout generation tools, as well as the most recent advances in analog layout-aware circuit sizing. The discussion includes different methods for automatic placement (a template-based Placer and an optimization-based Placer), a fully-automatic Router and an empirical-based Parasitic Extractor. The concepts and algorithms of all the modules are thoroughly described, enabling readers to reproduce the methodologies, improve the quality of their designs, or use them as starting point for a new tool. All the methods described are applied to practical examples for a 130nm design process, as well as placement and routing benchmark sets. Introduces readers to hierarchical combination of Pareto fronts of placements; Presents electromigration-aware routing with multilayer multiport terminal structures; Includes evolutionary multi-objective multi-constraint detailed Router; Enables parasitic extraction performed over a semi-complete layout. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Lourenço, Nuno. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Horta, Nuno. |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | https://doi.org/10.1007/978-3-319-34060-9 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | eBooks |
| 100 1# - AUTHOR NAME | |
| -- | (orcid)0000-0002-8251-1415 |
| -- | https://orcid.org/0000-0002-8251-1415 |
| 264 #1 - | |
| -- | Cham : |
| -- | Springer International Publishing : |
| -- | Imprint: Springer, |
| -- | 2017. |
| 336 ## - | |
| -- | text |
| -- | txt |
| -- | rdacontent |
| 337 ## - | |
| -- | computer |
| -- | c |
| -- | rdamedia |
| 338 ## - | |
| -- | online resource |
| -- | cr |
| -- | rdacarrier |
| 347 ## - | |
| -- | text file |
| -- | |
| -- | rda |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Electronic circuits. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Microprocessors. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Computer architecture. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Electronics. |
| 650 14 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Electronic Circuits and Systems. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Processor Architectures. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Electronics and Microelectronics, Instrumentation. |
| 912 ## - | |
| -- | ZDB-2-ENG |
| 912 ## - | |
| -- | ZDB-2-SXE |
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