Computer Architecture Techniques for Power-Efficiency (Record no. 84856)

000 -LEADER
fixed length control field 03834nam a22005055i 4500
001 - CONTROL NUMBER
control field 978-3-031-01721-6
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20240730163651.0
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 220601s2008 sz | s |||| 0|eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
ISBN 9783031017216
-- 978-3-031-01721-6
082 04 - CLASSIFICATION NUMBER
Call Number 621.3815
100 1# - AUTHOR NAME
Author Kaxiras, Stefanos.
245 10 - TITLE STATEMENT
Title Computer Architecture Techniques for Power-Efficiency
250 ## - EDITION STATEMENT
Edition statement 1st ed. 2008.
300 ## - PHYSICAL DESCRIPTION
Number of Pages XI, 207 p.
490 1# - SERIES STATEMENT
Series statement Synthesis Lectures on Computer Architecture,
505 0# - FORMATTED CONTENTS NOTE
Remark 2 Introduction -- Modeling, Simulation, and Measurement -- Using Voltage and Frequency Adjustments to Manage Dynamic Power -- Optimizing Capacitance and Switching Activity to Reduce Dynamic Power -- Managing Static (Leakage) Power -- Conclusions.
520 ## - SUMMARY, ETC.
Summary, etc In the last few years, power dissipation has become an important design constraint, on par with performance, in the design of new computer systems. Whereas in the past, the primary job of the computer architect was to translate improvements in operating frequency and transistor count into performance, now power efficiency must be taken into account at every step of the design process. While for some time, architects have been successful in delivering 40% to 50% annual improvement in processor performance, costs that were previously brushed aside eventually caught up. The most critical of these costs is the inexorable increase in power dissipation and power density in processors. Power dissipation issues have catalyzed new topic areas in computer architecture, resulting in a substantial body of work on more power-efficient architectures. Power dissipation coupled with diminishing performance gains, was also the main cause for the switch from single-core to multi-core architectures and aslowdown in frequency increase. This book aims to document some of the most important architectural techniques that were invented, proposed, and applied to reduce both dynamic power and static power dissipation in processors and memory hierarchies. A significant number of techniques have been proposed for a wide range of situations and this book synthesizes those techniques by focusing on their common characteristics. Table of Contents: Introduction / Modeling, Simulation, and Measurement / Using Voltage and Frequency Adjustments to Manage Dynamic Power / Optimizing Capacitance and Switching Activity to Reduce Dynamic Power / Managing Static (Leakage) Power / Conclusions.
700 1# - AUTHOR 2
Author 2 Martonosi, Margaret.
856 40 - ELECTRONIC LOCATION AND ACCESS
Uniform Resource Identifier https://doi.org/10.1007/978-3-031-01721-6
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type eBooks
264 #1 -
-- Cham :
-- Springer International Publishing :
-- Imprint: Springer,
-- 2008.
336 ## -
-- text
-- txt
-- rdacontent
337 ## -
-- computer
-- c
-- rdamedia
338 ## -
-- online resource
-- cr
-- rdacarrier
347 ## -
-- text file
-- PDF
-- rda
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Electronic circuits.
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Microprocessors.
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Computer architecture.
650 14 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Electronic Circuits and Systems.
650 24 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Processor Architectures.
830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE
-- 1935-3243
912 ## -
-- ZDB-2-SXSC

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