Multi-Core Cache Hierarchies (Record no. 84861)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 03724nam a22005175i 4500 |
| 001 - CONTROL NUMBER | |
| control field | 978-3-031-01734-6 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20240730163653.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 220601s2011 sz | s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9783031017346 |
| -- | 978-3-031-01734-6 |
| 082 04 - CLASSIFICATION NUMBER | |
| Call Number | 621.3815 |
| 100 1# - AUTHOR NAME | |
| Author | Balasubramonian, Rajeev. |
| 245 10 - TITLE STATEMENT | |
| Title | Multi-Core Cache Hierarchies |
| 250 ## - EDITION STATEMENT | |
| Edition statement | 1st ed. 2011. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Number of Pages | XVI, 137 p. |
| 490 1# - SERIES STATEMENT | |
| Series statement | Synthesis Lectures on Computer Architecture, |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Remark 2 | Basic Elements of Large Cache Design -- Organizing Data in CMP Last Level Caches -- Policies Impacting Cache Hit Rates -- Interconnection Networks within Large Caches -- Technology -- Concluding Remarks. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc | A key determinant of overall system performance and power dissipation is the cache hierarchy since access to off-chip memory consumes many more cycles and energy than on-chip accesses. In addition, multi-core processors are expected to place ever higher bandwidth demands on the memory system. All these issues make it important to avoid off-chip memory access by improving the efficiency of the on-chip cache. Future multi-core processors will have many large cache banks connected by a network and shared by many cores. Hence, many important problems must be solved: cache resources must be allocated across many cores, data must be placed in cache banks that are near the accessing core, and the most important data must be identified for retention. Finally, difficulties in scaling existing technologies require adapting to and exploiting new technology constraints. The book attempts a synthesis of recent cache research that has focused on innovations for multi-core processors. It is an excellent starting point for early-stage graduate students, researchers, and practitioners who wish to understand the landscape of recent cache research. The book is suitable as a reference for advanced computer architecture classes as well as for experienced researchers and VLSI engineers. Table of Contents: Basic Elements of Large Cache Design / Organizing Data in CMP Last Level Caches / Policies Impacting Cache Hit Rates / Interconnection Networks within Large Caches / Technology / Concluding Remarks. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Jouppi, Norman P. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Muralimanohar, Naveen. |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | https://doi.org/10.1007/978-3-031-01734-6 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | eBooks |
| 264 #1 - | |
| -- | Cham : |
| -- | Springer International Publishing : |
| -- | Imprint: Springer, |
| -- | 2011. |
| 336 ## - | |
| -- | text |
| -- | txt |
| -- | rdacontent |
| 337 ## - | |
| -- | computer |
| -- | c |
| -- | rdamedia |
| 338 ## - | |
| -- | online resource |
| -- | cr |
| -- | rdacarrier |
| 347 ## - | |
| -- | text file |
| -- | |
| -- | rda |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Electronic circuits. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Microprocessors. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Computer architecture. |
| 650 14 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Electronic Circuits and Systems. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Processor Architectures. |
| 830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE | |
| -- | 1935-3243 |
| 912 ## - | |
| -- | ZDB-2-SXSC |
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