A Primer on Hardware Prefetching (Record no. 84889)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 03684nam a22005055i 4500 |
| 001 - CONTROL NUMBER | |
| control field | 978-3-031-01743-8 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20240730163710.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 220601s2014 sz | s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9783031017438 |
| -- | 978-3-031-01743-8 |
| 082 04 - CLASSIFICATION NUMBER | |
| Call Number | 621.3815 |
| 100 1# - AUTHOR NAME | |
| Author | Falsafi, Babak. |
| 245 12 - TITLE STATEMENT | |
| Title | A Primer on Hardware Prefetching |
| 250 ## - EDITION STATEMENT | |
| Edition statement | 1st ed. 2014. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Number of Pages | XIV, 54 p. |
| 490 1# - SERIES STATEMENT | |
| Series statement | Synthesis Lectures on Computer Architecture, |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Remark 2 | Preface -- Introduction -- Instruction Prefetching -- Data Prefetching -- Concluding Remarks -- Bibliography -- Author Biographies . |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc | Since the 1970's, microprocessor-based digital platforms have been riding Moore's law, allowing for doubling of density for the same area roughly every two years. However, whereas microprocessor fabrication has focused on increasing instruction execution rate, memory fabrication technologies have focused primarily on an increase in capacity with negligible increase in speed. This divergent trend in performance between the processors and memory has led to a phenomenon referred to as the "Memory Wall." To overcome the memory wall, designers have resorted to a hierarchy of cache memory levels, which rely on the principal of memory access locality to reduce the observed memory access time and the performance gap between processors and memory. Unfortunately, important workload classes exhibit adverse memory access patterns that baffle the simple policies built into modern cache hierarchies to move instructions and data across cache levels. As such, processors often spend much time idling upon a demand fetch of memory blocks that miss in higher cache levels. Prefetching-predicting future memory accesses and issuing requests for the corresponding memory blocks in advance of explicit accesses-is an effective approach to hide memory access latency. There have been a myriad of proposed prefetching techniques, and nearly every modern processor includes some hardware prefetching mechanisms targeting simple and regular memory access patterns. This primer offers an overview of the various classes of hardware prefetchers for instructions and data proposed in the research literature, and presents examples of techniques incorporated into modern microprocessors. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Wenisch, Thomas F. |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | https://doi.org/10.1007/978-3-031-01743-8 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | eBooks |
| 264 #1 - | |
| -- | Cham : |
| -- | Springer International Publishing : |
| -- | Imprint: Springer, |
| -- | 2014. |
| 336 ## - | |
| -- | text |
| -- | txt |
| -- | rdacontent |
| 337 ## - | |
| -- | computer |
| -- | c |
| -- | rdamedia |
| 338 ## - | |
| -- | online resource |
| -- | cr |
| -- | rdacarrier |
| 347 ## - | |
| -- | text file |
| -- | |
| -- | rda |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Electronic circuits. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Microprocessors. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Computer architecture. |
| 650 14 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Electronic Circuits and Systems. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Processor Architectures. |
| 830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE | |
| -- | 1935-3243 |
| 912 ## - | |
| -- | ZDB-2-SXSC |
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