A Primer on Memory Persistency (Record no. 85217)

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fixed length control field 04356nam a22005295i 4500
001 - CONTROL NUMBER
control field 978-3-031-79205-2
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20240730164018.0
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
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020 ## - INTERNATIONAL STANDARD BOOK NUMBER
ISBN 9783031792052
-- 978-3-031-79205-2
082 04 - CLASSIFICATION NUMBER
Call Number 621.3815
100 1# - AUTHOR NAME
Author Gogte, Vaibhav.
245 12 - TITLE STATEMENT
Title A Primer on Memory Persistency
250 ## - EDITION STATEMENT
Edition statement 1st ed. 2022.
300 ## - PHYSICAL DESCRIPTION
Number of Pages XIX, 95 p.
490 1# - SERIES STATEMENT
Series statement Synthesis Lectures on Computer Architecture,
505 0# - FORMATTED CONTENTS NOTE
Remark 2 Preface -- Acknowledgments -- Persistent Memories -- Data Persistence -- Memory Persistency Models -- Hardware Mechanisms for Atomic Durability -- Programming Persistent Memory Systems -- Conclusion -- Bibliography -- Authors' Biographies.
520 ## - SUMMARY, ETC.
Summary, etc This book introduces readers to emerging persistent memory (PM) technologies that promise the performance of dynamic random-access memory (DRAM) with the durability of traditional storage media, such as hard disks and solid-state drives (SSDs). Persistent memories (PMs), such as Intel's Optane DC persistent memories, are commercially available today. Unlike traditional storage devices, PMs can be accessed over a byte-addressable load-store interface with access latency that is comparable to DRAM. Unfortunately, existing hardware and software systems are ill-equipped to fully avail the potential of these byte-addressable memory technologies as they have been designed to access traditional storage media over a block-based interface. Several mechanisms have been explored in the research literature over the past decade to design hardware and software systems that provide high-performance access to PMs.Because PMs are durable, they can retain data across failures, such as power failures andprogram crashes. Upon a failure, recovery mechanisms may inspect PM data, reconstruct state and resume program execution. Correct recovery of data requires that operations to the PM are properly ordered during normal program execution. Memory persistency models define the order in which memory operations are performed at the PM. Much like memory consistency models, memory persistency models may be relaxed to improve application performance. Several proposals have emerged recently to design memory persistency models for hardware and software systems and for high-level programming languages. These proposals differ in several key aspects; they relax PM ordering constraints, introduce varying programmability burden, and introduce differing granularity of failure atomicity for PM operations.This primer provides a detailed overview of the various classes of the memory persistency models, their implementations in hardware, programming languages and software systems proposed in the recent research literature, and the PM ordering techniques employed by modern processors.
700 1# - AUTHOR 2
Author 2 Kolli, Aasheesh.
700 1# - AUTHOR 2
Author 2 Wenisch, Thomas F.
856 40 - ELECTRONIC LOCATION AND ACCESS
Uniform Resource Identifier https://doi.org/10.1007/978-3-031-79205-2
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type eBooks
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-- Cham :
-- Springer International Publishing :
-- Imprint: Springer,
-- 2022.
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-- computer
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-- rdamedia
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-- online resource
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-- text file
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650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Electronic circuits.
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Microprocessors.
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Computer architecture.
650 14 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Electronic Circuits and Systems.
650 24 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Processor Architectures.
830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE
-- 1935-3243
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-- ZDB-2-SXSC

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