Layout Techniques in MOSFETs (Record no. 85812)

000 -LEADER
fixed length control field 03796nam a22005895i 4500
001 - CONTROL NUMBER
control field 978-3-031-02031-5
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20240730164633.0
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 220601s2016 sz | s |||| 0|eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
ISBN 9783031020315
-- 978-3-031-02031-5
082 04 - CLASSIFICATION NUMBER
Call Number 620
100 1# - AUTHOR NAME
Author Gimenez, Salvador Pinillos.
245 10 - TITLE STATEMENT
Title Layout Techniques in MOSFETs
250 ## - EDITION STATEMENT
Edition statement 1st ed. 2016.
300 ## - PHYSICAL DESCRIPTION
Number of Pages XI, 69 p.
490 1# - SERIES STATEMENT
Series statement Synthesis Lectures on Emerging Engineering Technologies,
505 0# - FORMATTED CONTENTS NOTE
Remark 2 Dedication -- Acknowledgments -- Introduction -- The Origin of the Innovative Layout Techniques for MOSFETS -- Diamond MOSFET (Hexagonal Gate Geometry) -- Octo Layout Style (Octagonal Gate Shape) for MOSFET -- Ellipsoidal Layout Style for MOSFET -- Fish Layout Style (".
520 ## - SUMMARY, ETC.
Summary, etc This book aims at describing in detail the different layout techniques for remarkably boosting the electrical performance and the ionizing radiation tolerance of planar Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs) without adding any costs to the current planar Complementary MOS (CMOS) integrated circuits (ICs) manufacturing processes. These innovative layout styles are based on pn junctions engineering between the drain/source and channel regions or simply MOSFET gate layout change. These interesting layout structures are capable of incorporating new effects in the MOSFET structures, such as the Longitudinal Corner Effect (LCE), the Parallel connection of MOSFETs with Different Channel Lengths Effect (PAMDLE), the Deactivation of the Parallel MOSFETs in the Bird's Beak Regions (DEPAMBBRE), and the Drain Leakage Current Reduction Effect (DLECRE), which are still seldom explored by the semiconductor and CMOS ICs industries. Several three-dimensional (3D) numerical simulations and experimental works are referenced in this book to show how these layout techniques can help the designers to reach the analog and digital CMOS ICs specifications with no additional cost. Furthermore, the electrical performance and ionizing radiation robustness of the analog and digital CMOS ICs can significantly be increased by using this gate layout approach.
856 40 - ELECTRONIC LOCATION AND ACCESS
Uniform Resource Identifier https://doi.org/10.1007/978-3-031-02031-5
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type eBooks
264 #1 -
-- Cham :
-- Springer International Publishing :
-- Imprint: Springer,
-- 2016.
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-- text
-- txt
-- rdacontent
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-- computer
-- c
-- rdamedia
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-- online resource
-- cr
-- rdacarrier
347 ## -
-- text file
-- PDF
-- rda
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Engineering.
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Electrical engineering.
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Electronic circuits.
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Computers.
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Materials science.
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Surfaces (Technology).
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Thin films.
650 14 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Technology and Engineering.
650 24 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Electrical and Electronic Engineering.
650 24 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Electronic Circuits and Systems.
650 24 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Computer Hardware.
650 24 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Materials Science.
650 24 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Surfaces, Interfaces and Thin Film.
830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE
-- 2381-1439
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-- ZDB-2-SXSC

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