Data Orchestration in Deep Learning Accelerators (Record no. 86128)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 03750nam a22005535i 4500 |
| 001 - CONTROL NUMBER | |
| control field | 978-3-031-01767-4 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20240730165141.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 220601s2020 sz | s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9783031017674 |
| -- | 978-3-031-01767-4 |
| 082 04 - CLASSIFICATION NUMBER | |
| Call Number | 621.3815 |
| 100 1# - AUTHOR NAME | |
| Author | Krishna, Tushar. |
| 245 10 - TITLE STATEMENT | |
| Title | Data Orchestration in Deep Learning Accelerators |
| 250 ## - EDITION STATEMENT | |
| Edition statement | 1st ed. 2020. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Number of Pages | XVII, 146 p. |
| 490 1# - SERIES STATEMENT | |
| Series statement | Synthesis Lectures on Computer Architecture, |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Remark 2 | Preface -- Acknowledgments -- Introduction to Data Orchestration -- Dataflow and Data Reuse -- Buffer Hierarchies -- Networks-on-Chip -- Putting it Together: Architecting a DNN Accelerator -- Modeling Accelerator Design Space -- Orchestrating Compressed-Sparse Data -- Conclusions -- Bibliography -- Authors' Biographies. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc | This Synthesis Lecture focuses on techniques for efficient data orchestration within DNN accelerators. The End of Moore's Law, coupled with the increasing growth in deep learning and other AI applications has led to the emergence of custom Deep Neural Network (DNN) accelerators for energy-efficient inference on edge devices. Modern DNNs have millions of hyper parameters and involve billions of computations; this necessitates extensive data movement from memory to on-chip processing engines. It is well known that the cost of data movement today surpasses the cost of the actual computation; therefore, DNN accelerators require careful orchestration of data across on-chip compute, network, and memory elements to minimize the number of accesses to external DRAM. The book covers DNN dataflows, data reuse, buffer hierarchies, networks-on-chip, and automated design-space exploration. It concludes with data orchestration challenges with compressed and sparse DNNs and future trends. The target audience is students, engineers, and researchers interested in designing high-performance and low-energy accelerators for DNN inference. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Kwon, Hyoukjun. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Parashar, Angshuman. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Pellauer, Michael. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Samajdar, Ananda. |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | https://doi.org/10.1007/978-3-031-01767-4 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | eBooks |
| 264 #1 - | |
| -- | Cham : |
| -- | Springer International Publishing : |
| -- | Imprint: Springer, |
| -- | 2020. |
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| -- | text |
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| -- | rdacontent |
| 337 ## - | |
| -- | computer |
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| -- | rdamedia |
| 338 ## - | |
| -- | online resource |
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| -- | rdacarrier |
| 347 ## - | |
| -- | text file |
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| -- | rda |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Electronic circuits. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Microprocessors. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Computer architecture. |
| 650 14 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Electronic Circuits and Systems. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Processor Architectures. |
| 830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE | |
| -- | 1935-3243 |
| 912 ## - | |
| -- | ZDB-2-SXSC |
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