Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation (Record no. 89211)

000 -LEADER
fixed length control field 05011nam a22006615i 4500
001 - CONTROL NUMBER
control field 978-3-540-32080-7
003 - CONTROL NUMBER IDENTIFIER
control field DE-He213
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20240730174014.0
007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION
fixed length control field cr nn 008mamaa
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 100929s2005 gw | s |||| 0|eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9783540320807
-- 978-3-540-32080-7
024 7# - OTHER STANDARD IDENTIFIER
Standard number or code 10.1007/11556930
Source of number or code doi
050 #4 - LIBRARY OF CONGRESS CALL NUMBER
Classification number QA76.9.L63
050 #4 - LIBRARY OF CONGRESS CALL NUMBER
Classification number TK7888.4
072 #7 - SUBJECT CATEGORY CODE
Subject category code UYF
Source bicssc
072 #7 - SUBJECT CATEGORY CODE
Subject category code COM036000
Source bisacsh
072 #7 - SUBJECT CATEGORY CODE
Subject category code UYF
Source thema
082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 621.395
Edition number 23
245 10 - TITLE STATEMENT
Title Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Medium [electronic resource] :
Remainder of title 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings /
Statement of responsibility, etc. edited by Vassilis Paliouras, Johan Vounckx, Diederik Verkest.
250 ## - EDITION STATEMENT
Edition statement 1st ed. 2005.
264 #1 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE
Place of production, publication, distribution, manufacture Berlin, Heidelberg :
Name of producer, publisher, distributor, manufacturer Springer Berlin Heidelberg :
-- Imprint: Springer,
Date of production, publication, distribution, manufacture, or copyright notice 2005.
300 ## - PHYSICAL DESCRIPTION
Extent XVI, 756 p.
Other physical details online resource.
336 ## - CONTENT TYPE
Content type term text
Content type code txt
Source rdacontent
337 ## - MEDIA TYPE
Media type term computer
Media type code c
Source rdamedia
338 ## - CARRIER TYPE
Carrier type term online resource
Carrier type code cr
Source rdacarrier
347 ## - DIGITAL FILE CHARACTERISTICS
File type text file
Encoding format PDF
Source rda
490 1# - SERIES STATEMENT
Series statement Programming and Software Engineering,
International Standard Serial Number 2945-9168 ;
Volume/sequential designation 3728
505 0# - FORMATTED CONTENTS NOTE
Formatted contents note Session 1: Low-Power Processors -- Session 2: Code Optimization for Low-Power -- Session 3: High-Level Design -- Session 4: Telecommunications and Signal Processing -- Session 5: Low-Power Circuits -- Session 6: System-on-Chip Design -- Session 7: Busses and Interconnections -- Session 8: Modeling -- Session 9: Design Automation -- Session 10: Low-Power Techniques -- Session 11: Memory and Register Files -- Poster Session 1: Applications -- Poster Session 2: Digital Circuits -- Poster Session 3: Analog and Physical Design -- Special Session: Digital Hearing Aids: Challenges and Solutions for Ultra Low Power -- Invited Talks.
520 ## - SUMMARY, ETC.
Summary, etc. Welcome to the proceedings of PATMOS 2005, the 15th in a series of international workshops.PATMOS2005wasorganizedbyIMECwithtechnicalco-sponsorshipfrom the IEEE Circuits and Systems Society. Over the years, PATMOS has evolved into an important European event, where - searchers from both industry and academia discuss and investigate the emerging ch- lenges in future and contemporary applications, design methodologies, and tools - quired for the developmentof upcominggenerationsof integrated circuits and systems. The technical program of PATMOS 2005 contained state-of-the-art technical contri- tions, three invited talks, a special session on hearing-aid design, and an embedded - torial. The technical program focused on timing, performance and power consumption, as well as architectural aspects with particular emphasis on modeling, design, char- terization, analysis and optimization in the nanometer era. The Technical Program Committee, with the assistance of additional expert revi- ers, selected the 74 papers to be presented at PATMOS. The papers were divided into 11 technical sessions and 3 poster sessions. As is always the case with the PATMOS workshops, the review process was anonymous, full papers were required, and several reviews were carried out per paper. Beyond the presentations of the papers, the PATMOS technical program was - riched by a series of speeches offered by world class experts, on important emerging research issues of industrial relevance. Prof. Jan Rabaey, Berkeley, USA, gave a talk on "Traveling the Wild Frontier of Ulta Low-Power Design", Dr. Sung Bae Park, S- sung, gave a presentation on "DVL (Deep Low Voltage): Circuits and Devices", Prof.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Logic design.
9 (RLIN) 3686
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Computers.
9 (RLIN) 8172
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Microprocessors.
9 (RLIN) 110705
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Computer architecture.
9 (RLIN) 3513
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Computer arithmetic and logic units.
9 (RLIN) 36750
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Computer-aided engineering.
9 (RLIN) 14016
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Electrical engineering.
9 (RLIN) 110706
650 14 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Logic Design.
9 (RLIN) 3686
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Hardware Performance and Reliability.
9 (RLIN) 32357
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Processor Architectures.
9 (RLIN) 110707
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Arithmetic and Logic Structures.
9 (RLIN) 36752
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Computer-Aided Engineering (CAD, CAE) and Design.
9 (RLIN) 31735
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Electrical and Electronic Engineering.
9 (RLIN) 110708
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Paliouras, Vassilis.
Relator term editor.
Relationship edt
-- http://id.loc.gov/vocabulary/relators/edt
9 (RLIN) 110709
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Vounckx, Johan.
Relator term editor.
Relationship edt
-- http://id.loc.gov/vocabulary/relators/edt
9 (RLIN) 110710
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Verkest, Diederik.
Relator term editor.
Relationship edt
-- http://id.loc.gov/vocabulary/relators/edt
9 (RLIN) 110711
710 2# - ADDED ENTRY--CORPORATE NAME
Corporate name or jurisdiction name as entry element SpringerLink (Online service)
9 (RLIN) 110712
773 0# - HOST ITEM ENTRY
Title Springer Nature eBook
776 08 - ADDITIONAL PHYSICAL FORM ENTRY
Relationship information Printed edition:
International Standard Book Number 9783540290131
776 08 - ADDITIONAL PHYSICAL FORM ENTRY
Relationship information Printed edition:
International Standard Book Number 9783540815884
830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE
Uniform title Programming and Software Engineering,
International Standard Serial Number 2945-9168 ;
Volume/sequential designation 3728
9 (RLIN) 110713
856 40 - ELECTRONIC LOCATION AND ACCESS
Uniform Resource Identifier <a href="https://doi.org/10.1007/11556930">https://doi.org/10.1007/11556930</a>
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-- ZDB-2-SXCS
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-- ZDB-2-LNC
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type eBooks-Lecture Notes in CS

No items available.