Reconfigurable Computing: Architectures, Tools and Applications (Record no. 97188)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 07571nam a22006255i 4500 |
| 001 - CONTROL NUMBER | |
| control field | 978-3-642-12133-3 |
| 003 - CONTROL NUMBER IDENTIFIER | |
| control field | DE-He213 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20240730202814.0 |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION | |
| fixed length control field | cr nn 008mamaa |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 100308s2010 gw | s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9783642121333 |
| -- | 978-3-642-12133-3 |
| 024 7# - OTHER STANDARD IDENTIFIER | |
| Standard number or code | 10.1007/978-3-642-12133-3 |
| Source of number or code | doi |
| 050 #4 - LIBRARY OF CONGRESS CALL NUMBER | |
| Classification number | TK5105.5-5105.9 |
| 072 #7 - SUBJECT CATEGORY CODE | |
| Subject category code | UKN |
| Source | bicssc |
| 072 #7 - SUBJECT CATEGORY CODE | |
| Subject category code | COM043000 |
| Source | bisacsh |
| 072 #7 - SUBJECT CATEGORY CODE | |
| Subject category code | UKN |
| Source | thema |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 004.6 |
| Edition number | 23 |
| 245 10 - TITLE STATEMENT | |
| Title | Reconfigurable Computing: Architectures, Tools and Applications |
| Medium | [electronic resource] : |
| Remainder of title | 6th International Symposium, ARC 2010, Bangkok, Thailand, March 17-19, 2010, Proceedings / |
| Statement of responsibility, etc. | edited by Phaophak Sirisuk, Fearghal Morgan, Tarek El-Ghazawi, Hideharu Amano. |
| 250 ## - EDITION STATEMENT | |
| Edition statement | 1st ed. 2010. |
| 264 #1 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE | |
| Place of production, publication, distribution, manufacture | Berlin, Heidelberg : |
| Name of producer, publisher, distributor, manufacturer | Springer Berlin Heidelberg : |
| -- | Imprint: Springer, |
| Date of production, publication, distribution, manufacture, or copyright notice | 2010. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | XIV, 450 p. 217 illus. |
| Other physical details | online resource. |
| 336 ## - CONTENT TYPE | |
| Content type term | text |
| Content type code | txt |
| Source | rdacontent |
| 337 ## - MEDIA TYPE | |
| Media type term | computer |
| Media type code | c |
| Source | rdamedia |
| 338 ## - CARRIER TYPE | |
| Carrier type term | online resource |
| Carrier type code | cr |
| Source | rdacarrier |
| 347 ## - DIGITAL FILE CHARACTERISTICS | |
| File type | text file |
| Encoding format | |
| Source | rda |
| 490 1# - SERIES STATEMENT | |
| Series statement | Theoretical Computer Science and General Issues, |
| International Standard Serial Number | 2512-2029 ; |
| Volume/sequential designation | 5992 |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | Keynotes (Abstracts) -- High-Performance Energy-Efficient Reconfigurable Accelerators/Co-processors for Tera-Scale Multi-core Microprocessors -- Process Variability and Degradation: New Frontier for Reconfigurable -- Towards Analytical Methods for FPGA Architecture Investigation -- Session 1: Architectures 1 -- Generic Systolic Array for Run-Time Scalable Cores -- Virtualization within a Parallel Array of Homogeneous Processing Units -- Feasibility Study of a Self-healing Hardware Platform -- Session 2: Applications 1 -- Application-Specific Signatures for Transactional Memory in Soft Processors -- Towards Rapid Dynamic Partial Reconfiguration in Video-Based Driver Assistance Systems -- Parametric Encryption Hardware Design -- A Reconfigurable Implementation of the Tate Pairing Computation over GF(2 m ) -- Session 3: Architectures 2 -- Application Specific FPGA Using Heterogeneous Logic Blocks -- Reconfigurable Communication Networks in a Parametric SIMD Parallel System on Chip -- A Dedicated Reconfigurable Architecture for Finite State Machines -- MEMS Dynamic Optically Reconfigurable Gate Array Usable under a Space Radiation Environment -- Session 4: Applications 2 -- An FPGA Accelerator for Hash Tree Generation in the Merkle Signature Scheme -- A Fused Hybrid Floating-Point and Fixed-Point Dot-Product for FPGAs -- Optimising Memory Bandwidth Use for Matrix-Vector Multiplication in Iterative Methods -- Design of a Financial Application Driven Multivariate Gaussian Random Number Generator for an FPGA -- Session 5: Design Tools 1 -- 3D Compaction: A Novel Blocking-Aware Algorithm for Online Hardware Task Scheduling and Placement on 2D Partially Reconfigurable Devices -- TROUTE: A Reconfigurability-Aware FPGA Router -- Space and Time Sharing of Reconfigurable Hardware for Accelerated Parallel Processing -- Routing-Aware Application Mapping Considering Steiner Points for Coarse-Grained Reconfigurable Architecture -- Session 6: Design Tools 2 -- Design Automation for Reconfigurable Interconnection Networks -- A Framework for Enabling Fault Tolerance in Reconfigurable Architectures -- QUAD - A Memory Access Pattern Analyser -- Hierarchical Loop Partitioning for Rapid Generation of Runtime Configurations -- Session 7: Applications 3 -- Reconfigurable Computing and Task Scheduling for Active Storage Service Processing -- A Reconfigurable Disparity Engine for Stereovision in Advanced Driver Assistance Systems -- A Modified Merging Approach for Datapath Configuration Time Reduction -- Posters -- Reconfigurable Computing Education in Computer Science -- Hardware Implementation of the Orbital Function for Quantum Chemistry Calculations -- Reconfigurable Polyphase Filter Bank Architecture for Spectrum Sensing -- Systolic Algorithm Mapping for Coarse Grained Reconfigurable Array Architectures -- A GMM-Based Speaker Identification System on FPGA -- An FPGA-Based Real-Time Event Sampler -- A Performance Evaluation of CUBE: One-Dimensional 512 FPGA Cluster -- An Analysis of Delay Based PUF Implementations on FPGA -- Comparison of Bit Serial Computation with Bit Parallel Computation for Reconfigurable Processor -- FPGA Implementation of QR Decomposition Using MGS Algorithm -- Memory-Centric Communication Architecture for Reconfigurable Computing -- Integrated Design Environment for Reconfigurable HPC -- Architecture-Aware Custom Instruction Generation for Reconfigurable Processors -- Cost and Performance Evaluation of a Noise Filter for Partitioning in Co-design Methodologies -- Towards a Tighter Integration of Generated and Custom-Made Hardware -- Pipelined Microprocessors Optimization andDebugging. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc. | Recon?gurable computing (RC) systems have generated considerable interest in the embedded and high-performance computing communities over the past two decades, with ?eld programmable gate arrays (FPGAs) as the leading techn- ogy at the helm of innovation in this discipline. Achieving orders of magnitude performance and power improvements using FPGAs over traditional microp- cessorsis not uncommon for well-suitedapplications. But even with two decades of research and technological advances, FPGA design still presents a subst- tial challenge and often necessitates hardware design expertise to exploit its true potential. Although the challenges to address the design productivity - sues are steep, the promise and the potential of the RC technology in terms of performance, power, size, and versatility continue to attract application design engineers and RC researchers alike. The International Symposium on Applied Recon?gurable Computing (ARC) aims to bring together researchers and practitioners of RC systems with an emphasis on practical applications and design methodologies of this promising technology. This year's ARC symposium (The sixth ARC symposium) was held in Bangkok, Thailand during March 17-19, 2010, and attracted papers in three primary focus areas:RC applications, RC architectures, and RC design meth- ologies. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Computer networks . |
| 9 (RLIN) | 31572 |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Software engineering. |
| 9 (RLIN) | 4138 |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Algorithms. |
| 9 (RLIN) | 3390 |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Computer science. |
| 9 (RLIN) | 9832 |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Computer programming. |
| 9 (RLIN) | 4169 |
| 650 14 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Computer Communication Networks. |
| 9 (RLIN) | 173133 |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Software Engineering. |
| 9 (RLIN) | 4138 |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Algorithms. |
| 9 (RLIN) | 3390 |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Theory of Computation. |
| 9 (RLIN) | 173134 |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Programming Techniques. |
| 9 (RLIN) | 173135 |
| 700 1# - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Sirisuk, Phaophak. |
| Relator term | editor. |
| Relationship | edt |
| -- | http://id.loc.gov/vocabulary/relators/edt |
| 9 (RLIN) | 173136 |
| 700 1# - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Morgan, Fearghal. |
| Relator term | editor. |
| Relationship | edt |
| -- | http://id.loc.gov/vocabulary/relators/edt |
| 9 (RLIN) | 173137 |
| 700 1# - ADDED ENTRY--PERSONAL NAME | |
| Personal name | El-Ghazawi, Tarek. |
| Relator term | editor. |
| Relationship | edt |
| -- | http://id.loc.gov/vocabulary/relators/edt |
| 9 (RLIN) | 173138 |
| 700 1# - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Amano, Hideharu. |
| Relator term | editor. |
| Relationship | edt |
| -- | http://id.loc.gov/vocabulary/relators/edt |
| 9 (RLIN) | 173139 |
| 710 2# - ADDED ENTRY--CORPORATE NAME | |
| Corporate name or jurisdiction name as entry element | SpringerLink (Online service) |
| 9 (RLIN) | 173140 |
| 773 0# - HOST ITEM ENTRY | |
| Title | Springer Nature eBook |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY | |
| Relationship information | Printed edition: |
| International Standard Book Number | 9783642121326 |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY | |
| Relationship information | Printed edition: |
| International Standard Book Number | 9783642121340 |
| 830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE | |
| Uniform title | Theoretical Computer Science and General Issues, |
| International Standard Serial Number | 2512-2029 ; |
| Volume/sequential designation | 5992 |
| 9 (RLIN) | 173141 |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | <a href="https://doi.org/10.1007/978-3-642-12133-3">https://doi.org/10.1007/978-3-642-12133-3</a> |
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| -- | ZDB-2-LNC |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | eBooks-Lecture Notes in CS |
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