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Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs [electronic resource] / by Brandon Noia, Krishnendu Chakrabarty.

By: Noia, Brandon [author.].
Contributor(s): Chakrabarty, Krishnendu [author.] | SpringerLink (Online service).
Material type: materialTypeLabelBookPublisher: Cham : Springer International Publishing : Imprint: Springer, 2014Description: XVIII, 245 p. 133 illus., 115 illus. in color. online resource.Content type: text Media type: computer Carrier type: online resourceISBN: 9783319023786.Subject(s): Engineering | Microprocessors | Semiconductors | Electronic circuits | Engineering | Circuits and Systems | Processor Architectures | SemiconductorsAdditional physical formats: Printed edition:: No titleDDC classification: 621.3815 Online resources: Click here to access online
Contents:
Introduction -- Wafer Stacking and 3D Memory Test -- Built-in Self-Test for TSVs -- Pre-Bond TSV Test Through TSV Probing -- Pre-Bond TSV Test Through TSV Probing -- Overcoming the Timing Overhead of Test Architectures on Inter-Die Critical Paths -- Post-Bond Test Wrappers and Emerging Test Standards -- Test-Architecture Optimization and Test Scheduling -- Conclusions.
In: Springer eBooksSummary: This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects.  The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain.  Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization.  Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.   • Provides a comprehensive guide to the challenges and solutions for the testing of TSV-based 3D stacked ICs; • Includes in-depth explanation of key test and design-for-test technologies, emerging standards, and test- architecture and test-schedule optimizations; • Encompasses all aspects of test as related to 3D ICs, including pre-bond and post-bond test as well as the test optimization and scheduling necessary to ensure that 3D testing remains cost-effective.  .
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Introduction -- Wafer Stacking and 3D Memory Test -- Built-in Self-Test for TSVs -- Pre-Bond TSV Test Through TSV Probing -- Pre-Bond TSV Test Through TSV Probing -- Overcoming the Timing Overhead of Test Architectures on Inter-Die Critical Paths -- Post-Bond Test Wrappers and Emerging Test Standards -- Test-Architecture Optimization and Test Scheduling -- Conclusions.

This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects.  The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain.  Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization.  Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.   • Provides a comprehensive guide to the challenges and solutions for the testing of TSV-based 3D stacked ICs; • Includes in-depth explanation of key test and design-for-test technologies, emerging standards, and test- architecture and test-schedule optimizations; • Encompasses all aspects of test as related to 3D ICs, including pre-bond and post-bond test as well as the test optimization and scheduling necessary to ensure that 3D testing remains cost-effective.  .

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