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Robust SRAM Designs and Analysis [electronic resource] / by Jawar Singh, Saraju P. Mohanty, Dhiraj K. Pradhan.

By: Singh, Jawar [author.].
Contributor(s): Mohanty, Saraju P [author.] | Pradhan, Dhiraj K [author.] | SpringerLink (Online service).
Material type: materialTypeLabelBookPublisher: New York, NY : Springer New York : Imprint: Springer, 2013Description: XII, 168 p. online resource.Content type: text Media type: computer Carrier type: online resourceISBN: 9781461408185.Subject(s): Engineering | Nanotechnology | Electronics | Microelectronics | Electronic circuits | Engineering | Circuits and Systems | Electronics and Microelectronics, Instrumentation | Nanotechnology and MicroengineeringAdditional physical formats: Printed edition:: No titleDDC classification: 621.3815 Online resources: Click here to access online
Contents:
Introduction to SRAM -- Design Metrics of SRAM Bitcell -- Single-ended SRAM Bitcell Design -- 2-Port SRAM Bitcell Design -- SRAM Bitcell Design Using Unidirectional Devices -- NBTI and its Effect on SRAM.
In: Springer eBooksSummary: This book provides a guide to Static Random Access Memory (SRAM) bitcell design and analysis to meet the nano-regime challenges for CMOS devices and emerging devices, such as Tunnel FETs. Since process variability is an ongoing challenge in large memory arrays, this book highlights the most popular SRAM bitcell topologies (benchmark circuits) that mitigate variability, along with exhaustive analysis. Experimental simulation setups are also included, which cover nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis. Emphasis is placed throughout the book on the various trade-offs for achieving a best SRAM bitcell design. Provides a complete and concise introduction to SRAM bitcell design and analysis; Offers techniques to face nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis; Includes simulation set-ups for extracting different design metrics for CMOS technology and emerging devices; Emphasizes different trade-offs for achieving the best possible SRAM bitcell design.
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Introduction to SRAM -- Design Metrics of SRAM Bitcell -- Single-ended SRAM Bitcell Design -- 2-Port SRAM Bitcell Design -- SRAM Bitcell Design Using Unidirectional Devices -- NBTI and its Effect on SRAM.

This book provides a guide to Static Random Access Memory (SRAM) bitcell design and analysis to meet the nano-regime challenges for CMOS devices and emerging devices, such as Tunnel FETs. Since process variability is an ongoing challenge in large memory arrays, this book highlights the most popular SRAM bitcell topologies (benchmark circuits) that mitigate variability, along with exhaustive analysis. Experimental simulation setups are also included, which cover nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis. Emphasis is placed throughout the book on the various trade-offs for achieving a best SRAM bitcell design. Provides a complete and concise introduction to SRAM bitcell design and analysis; Offers techniques to face nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis; Includes simulation set-ups for extracting different design metrics for CMOS technology and emerging devices; Emphasizes different trade-offs for achieving the best possible SRAM bitcell design.

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