Central Library

Normal view MARC view ISBD view

Transient-induced latchup in CMOS integrated circuits / Ming-Dou Ker and Sheng-Fu Hsu.

By: Ker, Ming-Dou [author.].
Contributor(s): Hsu, Sheng-Fu | John Wiley & Sons [publisher.] | IEEE Xplore (Online service) [distributor.].
Material type: materialTypeLabelBookPublisher: Singapore ; Wiley, c2009Distributor: [Piscataqay, New Jersey] : IEEE Xplore, [2010]Description: 1 PDF (xiii, 249 pages) : illustrations.Content type: text Media type: electronic Carrier type: online resourceISBN: 9780470824092.Subject(s): Metal oxide semiconductors, Complementary -- Defects | Metal oxide semiconductors, Complementary -- Reliability | CMOS integrated circuits | CMOS process | CMOS technology | Clamps | Conferences | Current measurement | Damping | Electric breakdown | Electrical resistance measurement | Electrostatic discharge | Frequency measurement | Guidelines | Indexes | Integrated circuit modeling | Integrated circuit reliability | Inverters | Junctions | Layout | Logic gates | MOS devices | Noise | Performance evaluation | Pins | Pulse measurements | Resistance | Robustness | Semiconductor device modeling | Stress | System-on-a-chip | Testing | Thyristors | Time frequency analysis | Transient analysis | Voltage control | Voltage measurementGenre/Form: Electronic books.Additional physical formats: Print version:: No titleDDC classification: 621.39/5 Online resources: Abstract with links to resource Also available in print.
Contents:
Physical Mechanism of TLU under the System-Level ESD Test -- Component-Level Measurement for TLU under System-Level ESD Considerations -- TLU Dependency on Power-Pin Damping Frequency and Damping Factor in CMOS Integrated Circuits -- TLU in CMOS ICs in the Electrical Fast Transient Test -- Methodology on Extracting Compact Layout Rules for Latchup Prevention -- Special Layout Issues for Latchup Prevention -- TLU Prevention in Power-Rail ESD Clamp Circuits -- Appendix A: Practical Application Extractions of Latchup Design Rules in a 0.18-mm 1.8 V/3.3V Silicided CMOS Process.
Summary: "Transient-Induced Latchup in CMOS Integrated Circuits equips the practicing engineer with all the tools needed to address this regularly occurring problem while becoming more proficient at IC layout. Ker and Hsu introduce the phenomenon and basic physical mechanism of latchup, explaining the critical issues that have resurfaced for CMOS technologies. Once readers can gain an understanding of the standard practices for TLU, Ker and Hsu discuss the physical mechanism of TLU under a system-level ESD test, while introducing an efficient component-level TLU measurement setup. The authors then present experimental methodologies to extract safe and area-efficient compact layout rules for latchup prevention, including layout rules for I/O cells, internal circuits, and between I/O and internal circuits. The book concludes with an appendix giving a practical example of extracting layout rules and guidelines for latchup prevention in a 0.18-micrometer 1.8V/3.3V silicided CMOS process."--Publisher's description.
    average rating: 0.0 (0 votes)
No physical items for this record

Includes bibliographical references and index.

Physical Mechanism of TLU under the System-Level ESD Test -- Component-Level Measurement for TLU under System-Level ESD Considerations -- TLU Dependency on Power-Pin Damping Frequency and Damping Factor in CMOS Integrated Circuits -- TLU in CMOS ICs in the Electrical Fast Transient Test -- Methodology on Extracting Compact Layout Rules for Latchup Prevention -- Special Layout Issues for Latchup Prevention -- TLU Prevention in Power-Rail ESD Clamp Circuits -- Appendix A: Practical Application Extractions of Latchup Design Rules in a 0.18-mm 1.8 V/3.3V Silicided CMOS Process.

Restricted to subscribers or individual electronic text purchasers.

"Transient-Induced Latchup in CMOS Integrated Circuits equips the practicing engineer with all the tools needed to address this regularly occurring problem while becoming more proficient at IC layout. Ker and Hsu introduce the phenomenon and basic physical mechanism of latchup, explaining the critical issues that have resurfaced for CMOS technologies. Once readers can gain an understanding of the standard practices for TLU, Ker and Hsu discuss the physical mechanism of TLU under a system-level ESD test, while introducing an efficient component-level TLU measurement setup. The authors then present experimental methodologies to extract safe and area-efficient compact layout rules for latchup prevention, including layout rules for I/O cells, internal circuits, and between I/O and internal circuits. The book concludes with an appendix giving a practical example of extracting layout rules and guidelines for latchup prevention in a 0.18-micrometer 1.8V/3.3V silicided CMOS process."--Publisher's description.

Also available in print.

Mode of access: World Wide Web

Made available online by Ebrary.

Description based on PDF viewed 12/21/2015.

There are no comments for this item.

Log in to your account to post a comment.