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Timing Performance of Nanometer Digital Circuits Under Process Variations [electronic resource] / by Victor Champac, Jose Garcia Gervacio.

By: Champac, Victor [author.].
Contributor(s): Garcia Gervacio, Jose [author.] | SpringerLink (Online service).
Material type: materialTypeLabelBookSeries: Frontiers in Electronic Testing: 39Publisher: Cham : Springer International Publishing : Imprint: Springer, 2018Edition: 1st ed. 2018.Description: XVIII, 185 p. 116 illus., 91 illus. in color. online resource.Content type: text Media type: computer Carrier type: online resourceISBN: 9783319754659.Subject(s): Electronic circuits | Microprocessors | Computer architecture | Electronics | Electronic Circuits and Systems | Processor Architectures | Electronics and Microelectronics, InstrumentationAdditional physical formats: Printed edition:: No title; Printed edition:: No title; Printed edition:: No titleDDC classification: 621.3815 Online resources: Click here to access online
Contents:
Introduction -- Mathematical Fundamentals -- Process Variations -- Gate delay under process variations -- Path Delay Under Process Variations -- Circuit Analysis under Process Variations -- FinFET Technology and design issues.
In: Springer Nature eBookSummary: This book discusses the digital design of integrated circuits under process variations, with a focus on design-time solutions. The authors describe a step-by-step methodology, going from logic gates to logic paths to the circuit level. Topics are presented in comprehensively, without overwhelming use of analytical formulations. Emphasis is placed on providing digital designers with understanding of the sources of process variations, their impact on circuit performance and tools for improving their designs to comply with product specifications. Various circuit-level “design hints” are highlighted, so that readers can use then to improve their designs. A special treatment is devoted to unique design issues and the impact of process variations on the performance of FinFET based circuits. This book enables readers to make optimal decisions at design time, toward more efficient circuits, with better yield and higher reliability.
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Introduction -- Mathematical Fundamentals -- Process Variations -- Gate delay under process variations -- Path Delay Under Process Variations -- Circuit Analysis under Process Variations -- FinFET Technology and design issues.

This book discusses the digital design of integrated circuits under process variations, with a focus on design-time solutions. The authors describe a step-by-step methodology, going from logic gates to logic paths to the circuit level. Topics are presented in comprehensively, without overwhelming use of analytical formulations. Emphasis is placed on providing digital designers with understanding of the sources of process variations, their impact on circuit performance and tools for improving their designs to comply with product specifications. Various circuit-level “design hints” are highlighted, so that readers can use then to improve their designs. A special treatment is devoted to unique design issues and the impact of process variations on the performance of FinFET based circuits. This book enables readers to make optimal decisions at design time, toward more efficient circuits, with better yield and higher reliability.

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