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ASIC Design and Synthesis [electronic resource] : RTL Design Using Verilog / by Vaibbhav Taraate.

By: Taraate, Vaibbhav [author.].
Contributor(s): SpringerLink (Online service).
Material type: materialTypeLabelBookPublisher: Singapore : Springer Nature Singapore : Imprint: Springer, 2021Edition: 1st ed. 2021.Description: XXI, 330 p. 311 illus., 184 illus. in color. online resource.Content type: text Media type: computer Carrier type: online resourceISBN: 9789813346420.Subject(s): Electronic circuits | Microprogramming  | Logic design | Electronic Circuits and Systems | Control Structures and Microprogramming | Logic DesignAdditional physical formats: Printed edition:: No title; Printed edition:: No title; Printed edition:: No titleDDC classification: 621.3815 Online resources: Click here to access online
Contents:
Chapter 1. Introduction -- Chapter 2. Design using CMOS -- Chapter 3. ASIC design synthesis for combinational design (RTL using VHDL) -- Chapter 4. ASIC Design and synthesis of complex combinational logic (RTL using VHDL) -- Chapter 5. ASIC Design and synthesis of sequential logic (RTL using VHDL) -- Chapter 6. ASIC design guidelines -- Chapter 7. ASIC RTL Verification -- Chapter 8. FSM using VHDL and synthesis -- Chapter 9. ASIC design improvement techniques -- Chapter 10. ASIC Synthesis using Synopsys DC -- Chapter 11. Design for Testability -- Chapter 12. Static timing analysis -- Chapter 13. Multiple Clock domain designs -- Chapter 14. Low power ASIC design -- Chapter 15. ASIC Physical design.
In: Springer Nature eBookSummary: This book describes simple to complex ASIC design practical scenarios using Verilog. It builds a story from the basic fundamentals of ASIC designs to advanced RTL design concepts using Verilog. Looking at current trends of miniaturization, the contents provide practical information on the issues in ASIC design and synthesis using Synopsys DC and their solution. The book explains how to write efficient RTL using Verilog and how to improve design performance. It also covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies. The contents of this book will be useful to practicing hardware engineers, students, and hobbyists looking to learn about ASIC design and synthesis.
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Chapter 1. Introduction -- Chapter 2. Design using CMOS -- Chapter 3. ASIC design synthesis for combinational design (RTL using VHDL) -- Chapter 4. ASIC Design and synthesis of complex combinational logic (RTL using VHDL) -- Chapter 5. ASIC Design and synthesis of sequential logic (RTL using VHDL) -- Chapter 6. ASIC design guidelines -- Chapter 7. ASIC RTL Verification -- Chapter 8. FSM using VHDL and synthesis -- Chapter 9. ASIC design improvement techniques -- Chapter 10. ASIC Synthesis using Synopsys DC -- Chapter 11. Design for Testability -- Chapter 12. Static timing analysis -- Chapter 13. Multiple Clock domain designs -- Chapter 14. Low power ASIC design -- Chapter 15. ASIC Physical design.

This book describes simple to complex ASIC design practical scenarios using Verilog. It builds a story from the basic fundamentals of ASIC designs to advanced RTL design concepts using Verilog. Looking at current trends of miniaturization, the contents provide practical information on the issues in ASIC design and synthesis using Synopsys DC and their solution. The book explains how to write efficient RTL using Verilog and how to improve design performance. It also covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies. The contents of this book will be useful to practicing hardware engineers, students, and hobbyists looking to learn about ASIC design and synthesis.

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