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Finite State Machine Datapath Design, Optimization, and Implementation [electronic resource] / by Justin Davis, Robert Reese.

By: Davis, Justin [author.].
Contributor(s): Reese, Robert [author.] | SpringerLink (Online service).
Material type: materialTypeLabelBookSeries: Synthesis Lectures on Digital Circuits & Systems: Publisher: Cham : Springer International Publishing : Imprint: Springer, 2008Edition: 1st ed. 2008.Description: IX, 113 p. online resource.Content type: text Media type: computer Carrier type: online resourceISBN: 9783031797767.Subject(s): Engineering | Electronic circuits | Control engineering | Robotics | Automation | Computers | Technology and Engineering | Electronic Circuits and Systems | Control, Robotics, Automation | Computer HardwareAdditional physical formats: Printed edition:: No title; Printed edition:: No titleDDC classification: 620 Online resources: Click here to access online
Contents:
Calculating Maximum Clock Frequency -- Improving Design Performance -- Finite State Machine with Datapath (FSMD) Design -- Embedded Memory Usage in Finite State Machine with Datapath (FSMD) Designs.
In: Springer Nature eBookSummary: Finite State Machine Datapath Design, Optimization, and Implementation explores the design space of combined FSM/Datapath implementations. The lecture starts by examining performance issues in digital systems such as clock skew and its effect on setup and hold time constraints, and the use of pipelining for increasing system clock frequency. This is followed by definitions for latency and throughput, with associated resource tradeoffs explored in detail through the use of dataflow graphs and scheduling tables applied to examples taken from digital signal processing applications. Also, design issues relating to functionality, interfacing, and performance for different types of memories commonly found in ASICs and FPGAs such as FIFOs, single-ports, and dual-ports are examined. Selected design examples are presented in implementation-neutral Verilog code and block diagrams, with associated design files available as downloads for both Altera Quartus and Xilinx Virtex FPGA platforms. A working knowledge of Verilog, logic synthesis, and basic digital design techniques is required. This lecture is suitable as a companion to the synthesis lecture titled Introduction to Logic Synthesis using Verilog HDL. Table of Contents: Calculating Maximum Clock Frequency / Improving Design Performance / Finite State Machine with Datapath (FSMD) Design / Embedded Memory Usage in Finite State Machine with Datapath (FSMD) Designs.
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Calculating Maximum Clock Frequency -- Improving Design Performance -- Finite State Machine with Datapath (FSMD) Design -- Embedded Memory Usage in Finite State Machine with Datapath (FSMD) Designs.

Finite State Machine Datapath Design, Optimization, and Implementation explores the design space of combined FSM/Datapath implementations. The lecture starts by examining performance issues in digital systems such as clock skew and its effect on setup and hold time constraints, and the use of pipelining for increasing system clock frequency. This is followed by definitions for latency and throughput, with associated resource tradeoffs explored in detail through the use of dataflow graphs and scheduling tables applied to examples taken from digital signal processing applications. Also, design issues relating to functionality, interfacing, and performance for different types of memories commonly found in ASICs and FPGAs such as FIFOs, single-ports, and dual-ports are examined. Selected design examples are presented in implementation-neutral Verilog code and block diagrams, with associated design files available as downloads for both Altera Quartus and Xilinx Virtex FPGA platforms. A working knowledge of Verilog, logic synthesis, and basic digital design techniques is required. This lecture is suitable as a companion to the synthesis lecture titled Introduction to Logic Synthesis using Verilog HDL. Table of Contents: Calculating Maximum Clock Frequency / Improving Design Performance / Finite State Machine with Datapath (FSMD) Design / Embedded Memory Usage in Finite State Machine with Datapath (FSMD) Designs.

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