Mano, M. Morris Ciletti, Michael. D. <br/><br/>
Digital Design 

 - 4 
 - New Delhi  Pearson  2008 
 - p.622 
<br/><br/><label>ISBN: </label>9788131714508 
<br/><br/><label>Subjects--Topical Terms: </label> Asynchronous Sequential Logic  Gate Level Minimization  Registers and  Counters 
<br/><br/><label>Dewey Class. No.: </label>621.381958 M280