Soni, Deepraj. <br/><br/>
Hardware Architectures for Post-Quantum Digital Signature Schemes  [electronic resource] / 
by Deepraj Soni, Kanad Basu, Mohammed Nabeel, Najwa Aaraj, Marc Manzano, Ramesh Karri. 
 - 1st ed. 2021. 
 - XXII, 170 p. 68 illus., 66 illus. in color.  online resource. 
<br/><br/>Introduction -- qTESLA -- CRYSTALS –Dilithium -- MQDSS -- SPHINCS -- Luov -- Falcon -- Picnic -- GeMSS -- Power, Performance, Area, and Security (PPAS) Comparison of the PQC Algorithms -- Conclusions. 
<br/><br/> This book explores C-based design, implementation, and analysis of post-quantum cryptography (PQC) algorithms for signature generation and verification. The authors investigate NIST round 2 PQC algorithms for signature generation and signature verification from a hardware implementation perspective, especially focusing on C-based design, power-performance-area-security (PPAS) trade-offs and design flows targeting FPGAs and ASICs. Describes a comprehensive set of synthesizable c code base as well as the hardware implementations for the different types of PQC algorithms including lattice-based, code-based, and multivariate-based; Demonstrates the hardware (FPGA and ASIC) and hardware-software optimizations and trade-offs of the NIST round 2 signature-based PQC algorithms; Enables designers to build hardware implementations that are resilient to a variety of side-channels. 
<br/><br/><label>ISBN: </label>9783030576820 
<br/><br/><label>Standard No.: </label>10.1007/978-3-030-57682-0  doi 
<br/><br/><label>Subjects--Topical Terms: </label><br/>Electronic circuits.<br/>Cooperating objects (Computer systems).<br/>Microprocessors.<br/>Computer architecture.<br/>Electronic Circuits and Systems.<br/>Cyber-Physical Systems.<br/>Processor Architectures.
<br/><br/><label>LC Class. No.: </label>TK7867-7867.5 
<br/><br/><label>Dewey Class. No.: </label>621.3815