On-Chip Networks [electronic resource] /
by Natalie Enright, Li-shiuan Peh.
- 1st ed. 2009.
- IV, 141 p. online resource.
- Synthesis Lectures on Computer Architecture, 1935-3243 .
- Synthesis Lectures on Computer Architecture, .
Introduction -- Interface with System Architecture -- Topology -- Routing -- Flow Control -- Router Microarchitecture -- Conclusions.
With the ability to integrate a large number of cores on a single chip, research into on-chip networks to facilitate communication becomes increasingly important. On-chip networks seek to provide a scalable and high-bandwidth communication substrate for multi-core and many-core architectures. High bandwidth and low latency within the on-chip network must be achieved while fitting within tight area and power budgets. In this lecture, we examine various fundamental aspects of on-chip network design and provide the reader with an overview of the current state-of-the-art research in this field. Table of Contents: Introduction / Interface with System Architecture / Topology / Routing / Flow Control / Router Microarchitecture / Conclusions.