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Customizable Computing [electronic resource] / by Yu-Ting Chen, Jason Cong, Michael Gill, Glenn Reinman, Bingjun Xiao.

By: Chen, Yu-Ting [author.].
Contributor(s): Cong, Jason [author.] | Gill, Michael [author.] | Reinman, Glenn [author.] | Xiao, Bingjun [author.] | SpringerLink (Online service).
Material type: materialTypeLabelBookSeries: Synthesis Lectures on Computer Architecture: Publisher: Cham : Springer International Publishing : Imprint: Springer, 2015Edition: 1st ed. 2015.Description: XI, 106 p. online resource.Content type: text Media type: computer Carrier type: online resourceISBN: 9783031017483.Subject(s): Electronic circuits | Microprocessors | Computer architecture | Electronic Circuits and Systems | Processor ArchitecturesAdditional physical formats: Printed edition:: No title; Printed edition:: No titleDDC classification: 621.3815 Online resources: Click here to access online
Contents:
Acknowledgments -- Introduction -- Road Map -- Customization of Cores -- Loosely Coupled Compute Engines -- On-Chip Memory Customization -- Interconnect Customization -- Concluding Remarks -- Bibliography -- Authors' Biographies .
In: Springer Nature eBookSummary: Since the end of Dennard scaling in the early 2000s, improving the energy efficiency of computation has been the main concern of the research community and industry. The large energy efficiency gap between general-purpose processors and application-specific integrated circuits (ASICs) motivates the exploration of customizable architectures, where one can adapt the architecture to the workload. In this Synthesis lecture, we present an overview and introduction of the recent developments on energy-efficient customizable architectures, including customizable cores and accelerators, on-chip memory customization, and interconnect optimization. In addition to a discussion of the general techniques and classification of different approaches used in each area, we also highlight and illustrate some of the most successful design examples in each category and discuss their impact on performance and energy efficiency. We hope that this work captures the state-of-the-art research and development oncustomizable architectures and serves as a useful reference basis for further research, design, and implementation for large-scale deployment in future computing systems.
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Acknowledgments -- Introduction -- Road Map -- Customization of Cores -- Loosely Coupled Compute Engines -- On-Chip Memory Customization -- Interconnect Customization -- Concluding Remarks -- Bibliography -- Authors' Biographies .

Since the end of Dennard scaling in the early 2000s, improving the energy efficiency of computation has been the main concern of the research community and industry. The large energy efficiency gap between general-purpose processors and application-specific integrated circuits (ASICs) motivates the exploration of customizable architectures, where one can adapt the architecture to the workload. In this Synthesis lecture, we present an overview and introduction of the recent developments on energy-efficient customizable architectures, including customizable cores and accelerators, on-chip memory customization, and interconnect optimization. In addition to a discussion of the general techniques and classification of different approaches used in each area, we also highlight and illustrate some of the most successful design examples in each category and discuss their impact on performance and energy efficiency. We hope that this work captures the state-of-the-art research and development oncustomizable architectures and serves as a useful reference basis for further research, design, and implementation for large-scale deployment in future computing systems.

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