000			03345nam a22004935i 4500
001			978-1-4614-3269-2
003			DE-He213
005			20200420220225.0
007			cr nn 008mamaa
008			130507s2013 xxu| s |||| 0|eng d
020			_a9781461432692 _9978-1-4614-3269-2
024	7		_a10.1007/978-1-4614-3269-2 _2doi
050		4	_aTK7888.4
072		7	_aTJFC _2bicssc
072		7	_aTEC008010 _2bisacsh
082	0	4	_a621.3815 _223
100	1		_aGangadharan, Sridhar. _eauthor.
245	1	0	_aConstraining Designs for Synthesis and Timing Analysis _h[electronic resource] : _bA Practical Guide to Synopsys Design Constraints (SDC) / _cby Sridhar Gangadharan, Sanjay Churiwala.
264		1	_aNew York, NY : _bSpringer New York : _bImprint: Springer, _c2013.
300			_aXXVII, 226 p. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
505	0		_aIntroduction -- Synthesis Basics -- Timing Analysis and Constraints -- SDC Extensions through Tcl -- Clocks -- Generated Clocks -- Clock Groups -- Other Clock Characteristics -- Port Delays -- Completing Port Constraints -- False Paths -- Multi Cycle Paths -- Combinatorial Paths -- Modal Analysis -- Managing Your Constraints -- Miscellaneous SDC Commands -- XDC: Xilinx Extensions To SDC.
520			_aThis book serves as a hands-on guide to timing constraints in integrated circuit design.  Readers will learn to maximize performance of their IC designs, by specifying timing requirements correctly.  Coverage includes key aspects of the design flow impacted by timing constraints, including synthesis, static timing analysis and placement and routing.  Concepts needed for specifying timing requirements are explained in detail and then applied to specific stages in the design flow, all within the context of Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints.  �         Provides a hands-on guide to synthesis and timing analysis, using Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints; �         Includes key topics of interest to a synthesis, static timing analysis or  place and route engineer; �         Explains which constraints command to use for ease of maintenance and reuse, given several options possible to achieve the same effect on timing; �         Explains fundamental concepts and provides exact command syntax.
650		0	_aEngineering.
650		0	_aMicroprocessors.
650		0	_aElectronics.
650		0	_aMicroelectronics.
650		0	_aElectronic circuits.
650	1	4	_aEngineering.
650	2	4	_aCircuits and Systems.
650	2	4	_aElectronics and Microelectronics, Instrumentation.
650	2	4	_aProcessor Architectures.
700	1		_aChuriwala, Sanjay. _eauthor.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9781461432685
856	4	0	_uhttp://dx.doi.org/10.1007/978-1-4614-3269-2
912			_aZDB-2-ENG
942			_cEBK
999			_c52156 _d52156