000			03391nam a22004935i 4500
001			978-3-319-32759-4
003			DE-He213
005			20200420220227.0
007			cr nn 008mamaa
008			160621s2016 gw | s |||| 0|eng d
020			_a9783319327594 _9978-3-319-32759-4
024	7		_a10.1007/978-3-319-32759-4 _2doi
050		4	_aTK7888.4
072		7	_aTJFC _2bicssc
072		7	_aTEC008010 _2bisacsh
082	0	4	_a621.3815 _223
100	1		_aSpiridon, Silvian. _eauthor.
245	1	0	_aToward 5G Software Defined Radio Receiver Front-Ends _h[electronic resource] / _cby Silvian Spiridon.
264		1	_aCham : _bSpringer International Publishing : _bImprint: Springer, _c2016.
300			_aXVII, 96 p. 50 illus., 20 illus. in color. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
490	1		_aSpringerBriefs in Electrical and Computer Engineering, _x2191-8112
505	0		_aOverview of Wireless Communication in the Internet Age -- Defining the optimal architecture -- From High Level Standard Requirements to Circuit Level Electrical Specifications: A Standard Independent Approach -- Optimal Filter Partitioning -- Smart Gain Partitioning for Noise - Linearity Trade-Off Optimization -- SDRX Electrical Specifications -- A System Level Perspective of Modern Receiver Building Blocks -- Conclusions and Future Developers.
520			_aThis book introduces a new intuitive design methodology for the optimal design path for next-generation software defined radio front-ends (SDRXs). The methodology described empowers designers to "attack" the multi-standard environment in a parallel way rather than serially, providing a critical tool for any design methodology targeting 5G circuits and systems. Throughout the book the SDRX design follows the key wireless standards of the moment (i.e., GSM, WCDMA, LTE, Bluetooth, WLAN), since a receiver compatible with these standards is the most likely candidate for the first design iteration in a 5G deployment. The author explains the fundamental choice the designer has to make regarding the optimal channel selection: how much of the blockers/interferers will be filtered in the analog domain and how much will remain to be filtered in the digital domain. The system-level analysis the author describes entails the direct sampling architecture is treated as a particular case of mixer-based direct conversion architecture. This allows readers give a power consumption budget to determine how much filtering is required on the receive path, by considering the ADC performance characteristics and the corresponding blocker diagram.
650		0	_aEngineering.
650		0	_aElectronics.
650		0	_aMicroelectronics.
650		0	_aElectronic circuits.
650	1	4	_aEngineering.
650	2	4	_aCircuits and Systems.
650	2	4	_aSignal, Image and Speech Processing.
650	2	4	_aElectronics and Microelectronics, Instrumentation.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9783319327587
830		0	_aSpringerBriefs in Electrical and Computer Engineering, _x2191-8112
856	4	0	_uhttp://dx.doi.org/10.1007/978-3-319-32759-4
912			_aZDB-2-ENG
942			_cEBK
999			_c52257 _d52257