000 | 03834nam a22005055i 4500 | ||
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001 | 978-3-319-01997-0 | ||
003 | DE-He213 | ||
005 | 20200421111154.0 | ||
007 | cr nn 008mamaa | ||
008 | 141014s2015 gw | s |||| 0|eng d | ||
020 |
_a9783319019970 _9978-3-319-01997-0 |
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024 | 7 |
_a10.1007/978-3-319-01997-0 _2doi |
|
050 | 4 | _aTK7888.4 | |
072 | 7 |
_aTJFC _2bicssc |
|
072 | 7 |
_aTEC008010 _2bisacsh |
|
082 | 0 | 4 |
_a621.3815 _223 |
100 | 1 |
_aAlioto, Massimo. _eauthor. |
|
245 | 1 | 0 |
_aFlip-Flop Design in Nanometer CMOS _h[electronic resource] : _bFrom High Speed to Low Energy / _cby Massimo Alioto, Elio Consoli, Gaetano Palumbo. |
264 | 1 |
_aCham : _bSpringer International Publishing : _bImprint: Springer, _c2015. |
|
300 |
_aXV, 260 p. 123 illus., 5 illus. in color. _bonline resource. |
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336 |
_atext _btxt _2rdacontent |
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337 |
_acomputer _bc _2rdamedia |
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338 |
_aonline resource _bcr _2rdacarrier |
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347 |
_atext file _bPDF _2rda |
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505 | 0 | _aThe Logical Effort Method -- Design in the Energy-Delay Space -- Clocked Storage Elements -- Flip-Flop Optimized Design -- Analysis and Comparison in the Energy-Delay-Area Domain -- Energy Efficiency Versus Clock Slope -- Hold Time Issues and Impact of variations on Flip-Flop Topologies -- Ultra-Fast and Energy-Efficient Pulsed Latch Topologies. | |
520 | _aThis book provides a unified treatment of Flip-Flop design and selection in nanometer CMOS VLSI systems. The design aspects related to the energy-delay tradeoff in Flip-Flops are discussed, including their energy-optimal selection according to the targeted application, and the detailed circuit design in nanometer CMOS VLSI systems. Design strategies are derived in a coherent framework that includes explicitly nanometer effects, including leakage, layout parasitics and process/voltage/temperature variations, as main advances over the existing body of work in the field. The related design tradeoffs are explored in a wide range of applications and the related energy-performance targets. A wide range of existing and recently proposed Flip-Flop topologies are discussed. Theoretical foundations are provided to set the stage for the derivation of design guidelines, and emphasis is given on practical aspects and consequences of the presented results. Analytical models and derivations are introduced when needed to gain an insight into the inter-dependence of design parameters under practical constraints. This book serves as a valuable reference for practicing engineers working in the VLSI design area, and as text book for senior undergraduate, graduate and postgraduate students (already familiar with digital circuits and timing). • Provides a unified treatment of Flip-Flop design and energy/variation-aware selection in nanometer CMOS VLSI systems • Offers in-depth analysis of the impact of nanometer effects on design tradeoffs • Presents a comprehensive analysis, by considering more than 20 topologies covering all relevant classes of circuits • Uses a rigorous framework based on novel methodologies to include layout parasitics within the circuit design loop . | ||
650 | 0 | _aEngineering. | |
650 | 0 | _aMicroprocessors. | |
650 | 0 | _aElectronic circuits. | |
650 | 0 | _aNanotechnology. | |
650 | 1 | 4 | _aEngineering. |
650 | 2 | 4 | _aCircuits and Systems. |
650 | 2 | 4 | _aElectronic Circuits and Devices. |
650 | 2 | 4 | _aProcessor Architectures. |
650 | 2 | 4 | _aNanotechnology and Microengineering. |
700 | 1 |
_aConsoli, Elio. _eauthor. |
|
700 | 1 |
_aPalumbo, Gaetano. _eauthor. |
|
710 | 2 | _aSpringerLink (Online service) | |
773 | 0 | _tSpringer eBooks | |
776 | 0 | 8 |
_iPrinted edition: _z9783319019963 |
856 | 4 | 0 | _uhttp://dx.doi.org/10.1007/978-3-319-01997-0 |
912 | _aZDB-2-ENG | ||
942 | _cEBK | ||
999 |
_c53418 _d53418 |