000 03707nam a22004575i 4500
001 978-3-319-08753-5
003 DE-He213
005 20200421111653.0
007 cr nn 008mamaa
008 140724s2015 gw | s |||| 0|eng d
020 _a9783319087535
_9978-3-319-08753-5
024 7 _a10.1007/978-3-319-08753-5
_2doi
050 4 _aTK7888.4
072 7 _aTJFC
_2bicssc
072 7 _aTEC008010
_2bisacsh
082 0 4 _a621.3815
_223
100 1 _aChen, Weiwei.
_eauthor.
245 1 0 _aOut-of-order Parallel Discrete Event Simulation for Electronic System-level Design
_h[electronic resource] /
_cby Weiwei Chen.
264 1 _aCham :
_bSpringer International Publishing :
_bImprint: Springer,
_c2015.
300 _aXIX, 145 p. 51 illus., 41 illus. in color.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
505 0 _aIntroduction -- The ConcurrenC Model of Computation -- Synchronous Parallel Discrete Event Simulation -- Out-of-order Parallel Discrete Event Simulation -- Optimized Out-of-order Parallel Discrete Event Simulation -- Comparison and Outlook -- Utilizing the Parallel Simulation Infrastructure -- Conclusions.
520 _aThis book offers readers a set of new approaches and tools a set of tools and techniques for facing challenges in parallelization with design of embedded systems.  It provides an advanced parallel simulation infrastructure for efficient and effective system-level model validation and development so as to build better products in less time.  Since parallel discrete event simulation (PDES) has the potential to exploit the underlying parallel computational capability in today's multi-core simulation hosts, the author begins by reviewing the parallelization of discrete event simulation, identifying problems and solutions.  She then describes out-of-order parallel discrete event simulation (OoO PDES), a novel approach for efficient validation of system-level designs by aggressively exploiting the parallel capabilities of todays' multi-core PCs. This approach enables readers to design simulators that can fully exploit the parallel processing capability of the multi-core system to achieve fast speed simulation, without loss of simulation and timing accuracy. Based on this parallel simulation infrastructure, the author further describes automatic approaches that help the designer quickly to narrow down the debugging targets in faulty ESL models with parallelism.   • Provides an introduction to electronic system-level (ESL) design, along with background on simulation execution semantics for ESL models; • Discusses discrete event simulation, along with synchronous and out-of-order parallel discrete simulation approaches, including the underlying data structure, the scheduling algorithm, and the predictive static code analysis technique; • Includes guidelines for choosing among different simulation and diagnosis approaches for models with different features; • Presents the model analysis approaches to increase the observability for parallel ESL model development.
650 0 _aEngineering.
650 0 _aMicroprocessors.
650 0 _aElectronic circuits.
650 1 4 _aEngineering.
650 2 4 _aCircuits and Systems.
650 2 4 _aProcessor Architectures.
650 2 4 _aElectronic Circuits and Devices.
710 2 _aSpringerLink (Online service)
773 0 _tSpringer eBooks
776 0 8 _iPrinted edition:
_z9783319087528
856 4 0 _uhttp://dx.doi.org/10.1007/978-3-319-08753-5
912 _aZDB-2-ENG
942 _cEBK
999 _c54524
_d54524