000			03361nam a22005295i 4500
001			978-981-10-0800-9
003			DE-He213
005			20200421111702.0
007			cr nn 008mamaa
008			160406s2016 si | s |||| 0|eng d
020			_a9789811008009 _9978-981-10-0800-9
024	7		_a10.1007/978-981-10-0800-9 _2doi
050		4	_aT174.7
072		7	_aTDPB _2bicssc
072		7	_aTEC027000 _2bisacsh
082	0	4	_a620.5 _223
100	1		_aKaushik, B.K. _eauthor.
245	1	0	_aCrosstalk in Modern On-Chip Interconnects _h[electronic resource] : _bA FDTD Approach / _cby B.K. Kaushik, V. Ramesh Kumar, Amalendu Patnaik.
264		1	_aSingapore : _bSpringer Singapore : _bImprint: Springer, _c2016.
300			_aXV, 116 p. 71 illus. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
490	1		_aSpringerBriefs in Applied Sciences and Technology, _x2191-530X
505	0		_aIntroduction to On-chip Interconnects and Modeling -- Interconnect Modeling, CNT and GNR Structure, Properties and Characteristics -- FDTD Model for Crosstalk Analysis of CMOS Gate-Driven Coupled Copper Interconnects -- FDTD Model for Crosstalk Analysis of Multiwall Carbon Nanotube (MWCNT) Interconnects -- Crosstalk Modeling with Width Dependent MFP in MLGNR Interconnects Using FDTD Technique -- An Efficient US-FDTD Model for Crosstalk Analysis of On-chip Interconnects.
520			_aThe book provides accurate FDTD models for on-chip interconnects, covering most recent advancements in materials and design. Furthermore, depending on the geometry and physical configurations, different electrical equivalent models for CNT and GNR based interconnects are presented. Based on the electrical equivalent models the performance comparison among the Cu, CNT and GNR-based interconnects are also discussed in the book. The proposed models are validated with the HSPICE simulations. The book introduces the current research scenario in the modeling of on-chip interconnects. It presents the structure, properties, and characteristics of graphene based on-chip interconnects and the FDTD modeling of Cu based on-chip interconnects. The model considers the non-linear effects of CMOS driver as well as the transmission line effects of interconnect line that includes coupling capacitance and mutual inductance effects. In a more realistic manner, the proposed model includes the effect of width-dependent MFP of the MLGNR while taking into account the edge roughness.
650		0	_aEngineering.
650		0	_aNanotechnology.
650		0	_aElectronics.
650		0	_aMicroelectronics.
650		0	_aElectronic circuits.
650	1	4	_aEngineering.
650	2	4	_aNanotechnology and Microengineering.
650	2	4	_aElectronics and Microelectronics, Instrumentation.
650	2	4	_aCircuits and Systems.
700	1		_aKumar, V. Ramesh. _eauthor.
700	1		_aPatnaik, Amalendu. _eauthor.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9789811007996
830		0	_aSpringerBriefs in Applied Sciences and Technology, _x2191-530X
856	4	0	_uhttp://dx.doi.org/10.1007/978-981-10-0800-9
912			_aZDB-2-ENG
942			_cEBK
999			_c55036 _d55036