000			03232nam a22004695i 4500
001			978-3-319-09309-3
003			DE-He213
005			20200421111704.0
007			cr nn 008mamaa
008			140925s2015 gw | s |||| 0|eng d
020			_a9783319093093 _9978-3-319-09309-3
024	7		_a10.1007/978-3-319-09309-3 _2doi
050		4	_aTK7888.4
072		7	_aTJFC _2bicssc
072		7	_aTEC008010 _2bisacsh
082	0	4	_a621.3815 _223
100	1		_aDehbashi, Mehdi. _eauthor.
245	1	0	_aDebug Automation from Pre-Silicon to Post-Silicon _h[electronic resource] / _cby Mehdi Dehbashi, G�orschwin Fey.
264		1	_aCham : _bSpringer International Publishing : _bImprint: Springer, _c2015.
300			_aXIV, 171 p. 93 illus., 55 illus. in color. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
505	0		_aIntroduction -- Preliminaries -- Part I Debug of Design Bugs -- Automated Debugging for Logic Bugs -- Automated Debugging from Pre-Silicon to Post-Silicon -- Automated Debugging for Synchronization Bugs -- Part II Debug of Delay Faults -- Analyzing Timing Variations -- Automated Debugging for Timing Variations -- Efficient Automated Speedpath Debugging -- Part III Debug of Transactions -- Online Debug for NoC-Based Multiprocessor SoCs -- Summary and Outlook.
520			_aThis book describes automated debugging approaches for the bugs and the faults which appear in different abstraction levels of a hardware system. The authors employ a transaction-based debug approach to systems at the transaction-level, asserting the correct relation of transactions. The automated debug approach for design bugs finds the potential fault candidates at RTL and gate-level of a circuit. Debug techniques for logic bugs and synchronization bugs are demonstrated, enabling readers to localize the most difficult bugs. Debug automation for electrical faults (delay faults)finds the potentially failing speedpaths in a circuit at gate-level. The various debug approaches described achieve high diagnosis accuracy and reduce the debugging time, shortening the IC development cycle and increasing the productivity of designers. Describes a unified framework for debug automation used at both pre-silicon and post-silicon stages; Provides approaches for debug automation of a hardware system at different levels of abstraction, i.e., chip, gate-level, RTL and transaction level; Includes techniques for debug automation of design bugs and electrical faults, as well as an infrastructure to debug NoC-based multiprocessor SoCs.
650		0	_aEngineering.
650		0	_aMicroprocessors.
650		0	_aElectronic circuits.
650	1	4	_aEngineering.
650	2	4	_aCircuits and Systems.
650	2	4	_aProcessor Architectures.
650	2	4	_aElectronic Circuits and Devices.
700	1		_aFey, G�orschwin. _eauthor.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9783319093086
856	4	0	_uhttp://dx.doi.org/10.1007/978-3-319-09309-3
912			_aZDB-2-ENG
942			_cEBK
999			_c55132 _d55132