000			03442nam a22004815i 4500
001			978-3-319-03221-4
003			DE-He213
005			20200421111706.0
007			cr nn 008mamaa
008			140321s2014 gw | s |||| 0|eng d
020			_a9783319032214 _9978-3-319-03221-4
024	7		_a10.1007/978-3-319-03221-4 _2doi
050		4	_aTK7888.4
072		7	_aTJFC _2bicssc
072		7	_aTEC008010 _2bisacsh
082	0	4	_a621.3815 _223
100	1		_aVashchenko, Vladislav. _eauthor.
245	1	0	_aSystem Level ESD Protection _h[electronic resource] / _cby Vladislav Vashchenko, Mirko Scholz.
264		1	_aCham : _bSpringer International Publishing : _bImprint: Springer, _c2014.
300			_aXVIII, 320 p. 295 illus., 12 illus. in color. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
505	0		_aSystem 1 Level ESD design -- System Level Test Methods -- On-Chip System Level ESD Devices and Clamps -- Latch-up at System-Level Stress -- IC and Systemn ESD Co-Design.
520			_aThis book addresses key aspects of analog integrated circuits and systems design related to system level electrostatic discharge (ESD) protection.  It is an invaluable reference for anyone developing systems-on-chip (SoC) and systems-on-package (SoP), integrated with system-level ESD protection. The book focuses on both the design of semiconductor integrated circuit (IC) components with embedded, on-chip system level protection and IC-system co-design. The readers will be enabled to bring the system level ESD protection solutions to the level of integrated circuits, thereby reducing or completely eliminating the need for additional, discrete components on the printed circuit board (PCB) and meeting system-level ESD requirements. The authors take a systematic approach, based on IC-system ESD protection co-design. A detailed description of the available IC-level ESD testing methods is provided, together with a discussion of the correlation between IC-level and system-level ESD testing methods. The IC-level ESD protection design is demonstrated with representative case studies which are analyzed with various numerical simulations and ESD testing. The overall methodology for IC-system ESD co-design is presented as a step-by-step procedure that involves both ESD testing and numerical simulations.   • Provides a systematic approach for on-chip ESD protection design for system-level IC pins; • Describes a system-level co-design methodology, which uses external system level ESD protection components, together with on-chip ESD protection structure; • Includes a comprehensive description of wafer- level and component-level test methodologies and numerical simulations.
650		0	_aEngineering.
650		0	_aElectronic circuits.
650		0	_aElectronics.
650		0	_aMicroelectronics.
650	1	4	_aEngineering.
650	2	4	_aCircuits and Systems.
650	2	4	_aElectronic Circuits and Devices.
650	2	4	_aElectronics and Microelectronics, Instrumentation.
700	1		_aScholz, Mirko. _eauthor.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9783319032207
856	4	0	_uhttp://dx.doi.org/10.1007/978-3-319-03221-4
912			_aZDB-2-ENG
942			_cEBK
999			_c55253 _d55253