000 03982nam a22005055i 4500
001 978-1-4614-3467-2
003 DE-He213
005 20200421111838.0
007 cr nn 008mamaa
008 120823s2013 xxu| s |||| 0|eng d
020 _a9781461434672
_9978-1-4614-3467-2
024 7 _a10.1007/978-1-4614-3467-2
_2doi
050 4 _aTK7888.4
072 7 _aTJFC
_2bicssc
072 7 _aTEC008010
_2bisacsh
082 0 4 _a621.3815
_223
100 1 _aFigueiredo, Michael.
_eauthor.
245 1 0 _aReference-Free CMOS Pipeline Analog-to-Digital Converters
_h[electronic resource] /
_cby Michael Figueiredo, Jo�ao Goes, Guiomar Evans.
264 1 _aNew York, NY :
_bSpringer New York :
_bImprint: Springer,
_c2013.
300 _aXVI, 184 p.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aAnalog Circuits and Signal Processing
505 0 _aIntroduction -- General Overview of Pipeline Analog-to-Digital Converters -- Capacitor Mismatch-Insensitive Multiplying-DAC Topologies with Unity Feedback Factor -- Application of Circuit Enhancement Techniques to ADC Building Blocks -- Design of a 7-bit 1GS/s CMOS Two-Way Interleaved Pipeline ADC -- Integrated Prototypes and Experimental Results -- Conclusions.
520 _aThis book shows that digitally assisted analog-to-digital converters are not the only way to cope with poor analog performance caused by technology scaling. It describes various analog design techniques that enhance the area and power efficiency without employing any type of digital calibration circuitry. These techniques consist of self-biasing for PVT enhancement, inverter-based design for improved speed/power ratio, gain-of-two obtained by voltage sum instead of charge redistribution, and current-mode reference shifting instead of voltage reference shifting. Together, these techniques allow enhancing the area and power efficiency of the main building blocks of a multiplying digital-to-analog converter (MDAC) based stage, namely, the flash quantizer, the amplifier, and the switched capacitor network of the MDAC. Complementing the theoretical analyses of the various techniques, a power efficient operational transconductance amplifier is implemented and experimentally characterized. Furthermore, a medium-low resolution reference-free high-speed time-interleaved pipeline ADC employing all mentioned design techniques and circuits is presented, implemented and experimentally characterized. This ADC is said to be reference-free because it precludes any reference voltage, therefore saving power and area, as reference circuits are not necessary. Experimental results demonstrate the potential of the techniques which enabled the implementation of area and power efficient circuits. Describes various design techniques to enhance the power and area efficiency of building blocks for multiplying digital-to-analog converter (MDAC) based ADCs, such as Pipeline, Algorithmic, and multi-step Flash; Enables analog designers to enhance the performance of a range of circuits, without employing any type of digital assistance (calibration); Includes complete design flow of an ADC based on the proposed circuits and design techniques.
650 0 _aEngineering.
650 0 _aElectronics.
650 0 _aMicroelectronics.
650 0 _aElectronic circuits.
650 1 4 _aEngineering.
650 2 4 _aCircuits and Systems.
650 2 4 _aElectronics and Microelectronics, Instrumentation.
700 1 _aGoes, Jo�ao.
_eauthor.
700 1 _aEvans, Guiomar.
_eauthor.
710 2 _aSpringerLink (Online service)
773 0 _tSpringer eBooks
776 0 8 _iPrinted edition:
_z9781461434665
830 0 _aAnalog Circuits and Signal Processing
856 4 0 _uhttp://dx.doi.org/10.1007/978-1-4614-3467-2
912 _aZDB-2-ENG
942 _cEBK
999 _c55384
_d55384