000			03349nam a22004815i 4500
001			978-1-4614-1323-3
003			DE-He213
005			20200421111852.0
007			cr nn 008mamaa
008			150612s2015 xxu| s |||| 0|eng d
020			_a9781461413233 _9978-1-4614-1323-3
024	7		_a10.1007/978-1-4614-1323-3 _2doi
050		4	_aTK7888.4
072		7	_aTJFC _2bicssc
072		7	_aTEC008010 _2bisacsh
082	0	4	_a621.3815 _223
100	1		_aSaini, Sandeep. _eauthor.
245	1	0	_aLow Power Interconnect Design _h[electronic resource] / _cby Sandeep Saini.
264		1	_aNew York, NY : _bSpringer New York : _bImprint: Springer, _c2015.
300			_aXVII, 152 p. 111 illus., 12 illus. in color. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
505	0		_aPart I Basics of Interconnect Design -- Introduction to Interconnects -- CMOS Buffer -- Part II Buffer and Schmidt trigger Insertion Techniques for Low Power Interconnect Design -- Buffer Insertion as a Solution to Interconnect Issues -- Schmidt Trigger Approach -- Part III Bus Coding Techniques for Low Power Interconnect Design -- Bus Coding Techniques.
520			_aThis book provides practical solutions for delay and power reduction for on-chip interconnects and buses.  It provides an in depth description of the problem of signal delay and extra power consumption, possible solutions for delay and glitch removal, while considering the power reduction of the total system.  Coverage focuses on use of the Schmitt Trigger as an alternative approach to buffer insertion for delay and power reduction in VLSI interconnects. In the last section of the book, various bus coding techniques are discussed to minimize delay and power in address and data buses.   �         Provides practical solutions for delay and power reduction for on-chip interconnects and buses; �         Focuses on Deep Sub micron technology devices and interconnects; �         Offers in depth analysis of delay, including details regarding crosstalk and parasitics;  �         Describes use of the Schmitt Trigger as a versatile alternative approach to buffer insertion for delay and power reduction in VLSI interconnects; �         Provides detailed simulation results to support the theoretical discussions. �         Provides details of delay and power efficient bus coding techniques.
650		0	_aEngineering.
650		0	_aMicroprocessors.
650		0	_aElectronics.
650		0	_aMicroelectronics.
650		0	_aElectronic circuits.
650	1	4	_aEngineering.
650	2	4	_aCircuits and Systems.
650	2	4	_aElectronics and Microelectronics, Instrumentation.
650	2	4	_aProcessor Architectures.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9781461413226
856	4	0	_uhttp://dx.doi.org/10.1007/978-1-4614-1323-3
912			_aZDB-2-ENG
942			_cEBK
999			_c56177 _d56177