000 | 02902nam a22005055i 4500 | ||
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001 | 978-1-4614-0818-5 | ||
003 | DE-He213 | ||
005 | 20200421112035.0 | ||
007 | cr nn 008mamaa | ||
008 | 120731s2013 xxu| s |||| 0|eng d | ||
020 |
_a9781461408185 _9978-1-4614-0818-5 |
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024 | 7 |
_a10.1007/978-1-4614-0818-5 _2doi |
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050 | 4 | _aTK7888.4 | |
072 | 7 |
_aTJFC _2bicssc |
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072 | 7 |
_aTEC008010 _2bisacsh |
|
082 | 0 | 4 |
_a621.3815 _223 |
100 | 1 |
_aSingh, Jawar. _eauthor. |
|
245 | 1 | 0 |
_aRobust SRAM Designs and Analysis _h[electronic resource] / _cby Jawar Singh, Saraju P. Mohanty, Dhiraj K. Pradhan. |
264 | 1 |
_aNew York, NY : _bSpringer New York : _bImprint: Springer, _c2013. |
|
300 |
_aXII, 168 p. _bonline resource. |
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336 |
_atext _btxt _2rdacontent |
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337 |
_acomputer _bc _2rdamedia |
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338 |
_aonline resource _bcr _2rdacarrier |
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347 |
_atext file _bPDF _2rda |
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505 | 0 | _aIntroduction to SRAM -- Design Metrics of SRAM Bitcell -- Single-ended SRAM Bitcell Design -- 2-Port SRAM Bitcell Design -- SRAM Bitcell Design Using Unidirectional Devices -- NBTI and its Effect on SRAM. | |
520 | _aThis book provides a guide to Static Random Access Memory (SRAM) bitcell design and analysis to meet the nano-regime challenges for CMOS devices and emerging devices, such as Tunnel FETs. Since process variability is an ongoing challenge in large memory arrays, this book highlights the most popular SRAM bitcell topologies (benchmark circuits) that mitigate variability, along with exhaustive analysis. Experimental simulation setups are also included, which cover nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis. Emphasis is placed throughout the book on the various trade-offs for achieving a best SRAM bitcell design. Provides a complete and concise introduction to SRAM bitcell design and analysis; Offers techniques to face nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis; Includes simulation set-ups for extracting different design metrics for CMOS technology and emerging devices; Emphasizes different trade-offs for achieving the best possible SRAM bitcell design. | ||
650 | 0 | _aEngineering. | |
650 | 0 | _aNanotechnology. | |
650 | 0 | _aElectronics. | |
650 | 0 | _aMicroelectronics. | |
650 | 0 | _aElectronic circuits. | |
650 | 1 | 4 | _aEngineering. |
650 | 2 | 4 | _aCircuits and Systems. |
650 | 2 | 4 | _aElectronics and Microelectronics, Instrumentation. |
650 | 2 | 4 | _aNanotechnology and Microengineering. |
700 | 1 |
_aMohanty, Saraju P. _eauthor. |
|
700 | 1 |
_aPradhan, Dhiraj K. _eauthor. |
|
710 | 2 | _aSpringerLink (Online service) | |
773 | 0 | _tSpringer eBooks | |
776 | 0 | 8 |
_iPrinted edition: _z9781461408178 |
856 | 4 | 0 | _uhttp://dx.doi.org/10.1007/978-1-4614-0818-5 |
912 | _aZDB-2-ENG | ||
942 | _cEBK | ||
999 |
_c56338 _d56338 |